VLSI Programming [2IN35]

Year 2014-2015, Quart 4

Period:

BIS-1, CSE-1, ES-1, ES(EIT-EMS)-1

Credit points:

5 ects

Provided by:

Dept W&I, CS

Teachers:

Prof.dr. C.H. van Berkel, dr. R.H. Mak

Lab instructors:

M.Sc. Hrishikesh Salunkhe, M.Sc. Alok Lele

Enquiries

Prof.dr. C.H. van Berkel, dr. R.H. Mak

Instruction type:

a combination of lectures and lab-assignments

Examination:

homework assignments + report on lab work + oral examination

Study material:

Keshab K. Parhi:

VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999.
pdf slides with text book: html ,
same (local copies): Parhi2.pdf , Parhi3.pdf , Parhi4.pdf , Parhi5.pdf , Parhi6.pdf , Parhi7.pdf , Parhi8.pdf , Parhi9.pdf , Parhi10.pdf , Parhi11.pdf , Parhi13.pdf , Parhi14.pdf , Parhi15.pdf , Parhi16.pdf , Parhi17.pdf , Parhi18.pdf
Keshab K. Parhi, High-Level Algorithm and Architecture Transformations for DSP Synthesis. Journal of VLSI Signal Processing, 9, 121-143 (1995), Kluwer Academic Publishers, Boston.
Keshab K. Parhi and David G. Messerschmitt, Pipeline Interleaving and Parallelism in Recursive Digital Filters - Part I: Pipelining Using Scattered Look-Ahead and Decomposition. IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol. 37, No. 7, July 1989, pp 1099 - 1117.

Lecture slides:

Week 1: 2IN35slides1.pdf, 2IN35slides2.pdf
Week 2: 2IN35slides3.pdf,
Week 3: 2IN35slides4.pdf
Week 4: 2IN35slides5.pdf
Week 5: 2IN35slides6.pdf, 2IN35slides-systolic.pdf,
Week 6: AnswersSystolic2015.pdf (answers to T5)
Week 8: not yet available

Homework assignments:

Use Peach to hand in your homework!

Assignments T1 + T2: 2IN35-T1-T2.pdf. Deadline, Monday, May 11, 8:45
Assignments T3 + T4: 2IN35-T3-T4.pdf. Deadline, Monday, May 18, 8:45
Assignment T5: 2IN35-T5-systolic.pdf. Deadline, Tuesday, May 26, 13:45

Goals:

to acquire insight in the description, design, and optimization of fine-grained parallel computations;

to acquire insight in the (future) capabilities of VLSI as an implementation medium of parallel computations;

to acquire skills in the design of parallel computations and in their implementation on FPGAs.

Contents:

Massive parallelism is needed to exploit the huge and still increasing computational capabilities of Very Large Scale Integrated (VLSI) circuits. In this course:

we focus on fine-grained parallelism (not on networks of computers);
we assume that parallelism is by design (not by compilation);
we draw inspiration from consumer applications, such as digital TV, 3D TV, image processing, mobile phones, etc.;
we will use Field Programmable Arrays (FPGA) as fine-grained abstraction of VLSI for practical implementation.

Major elements of the course:

Classifications: linear/non-linear, time-(in)variant systems, 1D/2D.
Representations and formalisms: data flow graphs, state-space forms, transfer functions, vector-parallel programs, parallel programs.
Performance metrics and scalability: costs (silicon area), computation time (throughput), power consumption (energy).
Architectures: digital hardware, systolic arrays, VLIW, SIMD.
Design & optimization: (SW) pipelining, unfolding, retiming, re-use of partial results, vectorization, etc.
Implementation media: VLSI, FPGAs, (vector) DSPs.

Schedules:

For a detailed lecture schedule with topics, see 2IN35-2015-schedule.pdf
For the updated schedule, dd June 2, see 2IN35-2015-updated-schedule.pdf
For a reservation schedule of additional lab time, see not yet available

The oral examination schedule is given by the following table

Group Students Day Date Hour Location

7 de Bruin
Veens Thursday June, 25 13:45 MF6.067

15 Knieps
Gunnarsson Thursday June, 25 14:45 MF6.067

5 Jansen
Monday June, 29 13:45 MF6.067

1 Vrijdag
Vrijdag Monday June, 29 14:45 MF6.067

4 Lazzarotto
Zhou Monday June, 29 15:45 MF6.067

12 Liu
Lu Monday June, 29 16:45 MF6.067

6 Liu T.
Xue Tuesday June, 30 13:45 MF6.067

Tuesday June, 30 14:45 MF6.067

Tuesday June, 30 15:45 MF6.067

10 Wu
Zhang Tuesday June, 30 16:45 MF6.067

2 Bhupesh
Mundichiparakkal Monday July, 6 13:45 MF6.067

Monday July, 6 14:45 MF6.067

8 van Dalen
de Vaan Monday July, 6 15:45 MF6.067

Monday July, 6 16:45 MF6.067

14 Hulten
Hurks Tuesday July, 7 13:45 MF6.067

3 Nidhi Anantharajaiah
Khahn Tuesday July, 7 14:45 MF6.067

Group	Students	Day	Date	Hour	Location
7	de Bruin Veens	Thursday	June, 25	13:45	MF6.067
15	Knieps Gunnarsson	Thursday	June, 25	14:45	MF6.067
5	Jansen	Monday	June, 29	13:45	MF6.067
1	Vrijdag Vrijdag	Monday	June, 29	14:45	MF6.067
4	Lazzarotto Zhou	Monday	June, 29	15:45	MF6.067
12	Liu Lu	Monday	June, 29	16:45	MF6.067
6	Liu T. Xue	Tuesday	June, 30	13:45	MF6.067
		Tuesday	June, 30	14:45	MF6.067
		Tuesday	June, 30	15:45	MF6.067
10	Wu Zhang	Tuesday	June, 30	16:45	MF6.067
2	Bhupesh Mundichiparakkal	Monday	July, 6	13:45	MF6.067
		Monday	July, 6	14:45	MF6.067
8	van Dalen de Vaan	Monday	July, 6	15:45	MF6.067
		Monday	July, 6	16:45	MF6.067
14	Hulten Hurks	Tuesday	July, 7	13:45	MF6.067
3	Nidhi Anantharajaiah Khahn	Tuesday	July, 7	14:45	MF6.067

Swapping slots is allowed, but should be done by yourself and in mutual agreement between groups.
If you do so, you have to notify R.H. Mak in advance and ensure that your report is present in PEACH according to the deadline. Ensure that your reports comply with the guidelines given in the lectures.
ALL group members need to be present at the oral exam and each group member is FULLY ACCOUNTABLE for all reports handed in by the group, i.e., can be asked questions on any part of a report, also parts written by other group members.

Groups:

For an overview of the groups, including scores for homework and lab progress, see not yet available

Lab Classes:

Required software: see preparation.pdf , Beware, new version installed April 28, 2015.
For assignments and Lab work files, click LabWork

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