The 'Asynchronous' Bibliography

Ad Peeters

This version was generated on May 05, 2004 and contains 1757 items.

A. Abrial, J. Bouvier, P. Senn, M. Renaudin, and P. Vivet. A new contactless smartcard IC using an on-chip antenna and an asynchronous micro-controller. In Proc. European Solid-State Circuits Conference (ESSCIRC), September 2000. (PDF)
André Abrial, Jacky Bouvier, Marc Renaudin, Patrice Senn, and Pascal Vivet. A new contactless smart card IC using an on-chip antenna and an asynchronous microcontroller. IEEE Journal of Solid-State Circuits, 36(7):1101-1107, 2001.
A. J. Acosta, M. Bellido, M. Valencia, A. Barriga, R. Jiménez, and J. L. Huertas. New CMOS VLSI linear self-timed architectures. In Asynchronous Design Methodologies, pages 14-23. IEEE Computer Society Press, May 1995.
A. J. Acosta, R. Jiménez, A. Barriga, M. J. Bellido, M. Valencia, and J. L. Huertas. Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure. IEE Proceedings, Circuits, Devices and Systems, 145(4):247-253, August 1998.
Robert Adams and Tom Kwan. A stereo asynchronous digital sample-rate converter for digital audio. IEEE Journal of Solid-State Circuits, 29(4):481-488, April 1994.
F. Aeschlimann, E. Allier, L. Fesquet, and M. Renaudin. Asynchronous FIR filters: Towards a new digital processing chain. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 198-206. IEEE Computer Society Press, April 2004.
Morteza Afghahi and Christer Svensson. Performance of synchronous and asynchronous schemes for VLSI systems. IEEE Transactions on Computers, 41(7):858-872, July 1992.
F. Aghdasi and M. Bolton. Self-clocked asynchronous finite state machine design with PAL22IP6 device. Microprocessors and Microsystems, February 1991.
Farhad Aghdasi. Pass-transistor self-clocked asynchronous sequential circuits. In Proceedings of VLSI 91, pages 9.1.1-9.1.9, 1991.
Farhad Aghdasi. Synthesis of asynchronous sequential machines for VLSI applications. In International Conference on Concurrent Engineering and Electronic Design Automation (CEEDA), pages 55-59, March 1991.
Farhad Aghdasi. Asynchronous state machine synthesis using data driven clocks. In Proc. European Design Automation Conference (EURO-DAC), pages 9-14, Hamburg, Germany, September 1992. IEEE Computer Society Press.
Farhad Aghdasi. Self-clocked controllers--a practical example. In O. M. Strydom, editor, Proceedings of Computer Systems Symposium (COMPSYS-94), pages 67-74, October 1994.
J. Ahmed and S. G. Zaky. Asynchronous design in dynamic CMOS. In P. Thorburn and J. Quaiceo, editors, Canadian Conference on Electrical and Computer Engineering, volume 2, pages 528-531, 1997.
V. Akella and G. Gopalakrishnan. SHILPA: A high-level synthesis system for self-timed circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 587-591. IEEE Computer Society Press, November 1992. (PostScript)
Venkatesh Akella and Ganesh Gopalakrishnan. Specification and validation of control-intensive IC's in hopCP. IEEE Transactions on Software Engineering, 20(6):405-423, 1994.
Venkatesh Akella and Ganesh Gopalakrishnan. Flow analysis techniques in high level asynchronous circuit synthesis. Technical report, University of California, Davis, 1999. (PostScript)
V. Akella, N. H. Vaidya, and R. Redinbo. Limitations of VLSI implementation of delay-insensitive codes. In International Symposium on Fault-Tolerant Computing (FTCS), June 1996.
Venkatesh Akella, Nitin H. Vaidya, and G. Robert Redinbo. Asynchronous comparison-based decoders for delay-insensitive codes. IEEE Transactions on Computers, 47(7):802-811, July 1998.
Venkatesh Akella. An Integrated Framework for the Automatic Synthesis of Efficient Self-timed Circuits from Behavioral Specifications. PhD thesis, The University of Utah, 1992. (PostScript)
E. Allier, L. Fesquet, M. Renaudin, and G. Sicard. Low-power asynchronous A/D conversion. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2451 of Lecture Notes in Computer Science, September 2002.
E. Allier, G. Sicard, L. Fesquet, and M. Renaudin. A new class of asynchronous A/D converters based on time quantization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 196-205. IEEE Computer Society Press, May 2003.
Manish Amde, Ivan Blunno, and Christos P. Sotiriou. Automating the design of an asynchronous DLX microprocessor. In Proc. ACM/IEEE Design Automation Conference, pages 502-507, June 2003.
T. Amon and H. Hulgaard. Symbolic time separation of events. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 83-93, April 1999.
Tod Amon, Henrik Hulgaard, Steven M. Burns, and Gaetano Borriello. Algorithm for exact bounds on the time separation of events in concurrent systems. In Proc. International Conf. Computer Design (ICCD), pages 166-173, 1993. (PostScript)
T. S. Anantharaman. A delay insensitive regular expression recognizer. IEEE VLSI Technical Bulletin, 1(2), 1986.
A. de Angel and E. Swartzlander Jr. A new asynchronous multiplier using enable/disable CMOS differential logic. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
Anonymous. Science and the citizen. Scientific American, 228:43-44, 1973.
P. Antognetti, P. Danielli, A. De Gloria, P. Faraboschi, and M. Olivieri. A standard cell set for delay-insensitive VLSI design. In ASIC 92, 1992.
Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Cache design for an asynchronous vlsi risc processor. In Proceeding of Microelectronics 1995, pages 91-96, July 1995.
Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. The design of a fast asynchronous microprocessor. IEEE Technical Committee on Computer Architecture Newsletter, October 1995.
Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Technique for high speed asynchronous pipeline control. Electronics Letters, 32(21):1973-1974, October 1996.
S. Appleton, S. Morton, and M. Liebelt. High performance two-phase asynchronous pipelines. IEICE Transactions on Information and Systems, E80-D(3):287-295, March 1997.
Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. A new method for asynchronous pipeline control. In Proc. of the Great Lakes Symposium on VLSI, pages 100-104, 1997.
Sam S. Appleton, Shannon V. Morton, and Michael J. Liebelt. Two-phase asynchronous pipeline control. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 12-21. IEEE Computer Society Press, April 1997.
D. B. Armstrong, A. D. Friedman, and P. R. Menon. Realization of asynchronous sequential circuits without inserted delay elements. IEEE Transactions on Computers, C-17(2):129-134, February 1968.
Douglas B. Armstrong, Arthur D. Friedman, and Premachandran R. Menon. Design of asynchronous circuits assuming unbounded gate delays. IEEE Transactions on Computers, C-18(12):1110-1120, December 1969.
D. K. Arvind and Kristian Hildingsson. Power tradeoffs in asynchronous interfaces. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 151-158, July 2000.
D. K. Arvind and V. E. F. Rebello. Instruction-level parallelism in asynchronous processor architectures. In M. Moonen and F. Catthoor, editors, Proc. of the Third Int. Workshop on Algorithms and Parallel VLSI Architectures, pages 203-215. Elsevier Science Publishers, August 1994.
D. K. Arvind and V. E. F. Rebello. On the performance evaluation of asynchronous processor architectures. In P. Dowd and E. Gelenbe, editors, Proceedings of the 3rd International Workshop on Modelling Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS'95), pages 100-105, Durham, NC, USA, January 1995. IEEE Computer Society Press.
D. K. Arvind and V. E. F. Rebello. Optimisation of instruction schedules for micronet-based asynchronous processors. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
D. K. Arvind, R. D. Mullins, and V. E. F. Rebello. Micronets: A model for decentralising control in asynchronous processor architectures. In Asynchronous Design Methodologies, pages 190-199. IEEE Computer Society Press, May 1995.
P. Arya and E. H. Frank. The design and implementation of a VLSI multiplier generator. In The Fifth Australian and Pacific Region Microelectronics Conference, 1986.
Katsuhiko Asada and Hiroaki Terada. Hardware structure of a one-chip data-driven processor: Q-p. In Sartaj K. Sahni, editor, Proc. International Conference on Parallel Processing, pages 327-329, August 1987.
F. Asai, S. Komori, and T. Tamura. Self-timed design for a data-driven microprocessor. IEICE Transactions, E 74(11):3757-3765, November 1991.
Aaron Ashkinazy, Doug Edwards, Craig Farnsworth, Gary Gendel, and Shiv Sikand. Tools for validating asynchronous digital circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 12-21, November 1994. (PostScript)
Aaron Ashkinazy. Fault detection experiments for asynchronous sequential machines. In Annual Symposium on Switching and Automata Theory, pages 88-96. IEEE Computer Society Press, 1970.
International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC94), Salt Lake City, Utah, USA, November 1994. IEEE Computer Society Press.
Second Working Conference on Asynchronous Design Methodologies, London, England, UK, May 1995. IEEE Computer Society Press. (PDF)
Second International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC96), Aizu-Wakamatsu, Fukushima, Japan, March 1996. IEEE Computer Society Press. (PDF)
Third International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC97), Eindhoven, The Netherlands, April 1997. IEEE Computer Society Press. (PDF)
Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC98), San Diego, CA, USA, April 1998. IEEE Computer Society Press.
Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC99), Barcelona, Spain, April 1999. IEEE Computer Society Press.
Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC2000), Eilat, Israel, April 2000. IEEE Computer Society Press.
Seventh International Symposium on Asynchronous Circuits and Systems (ASYNC2001), Salt Lake City, Utah, USA, March 2001. IEEE Computer Society Press. (PDF)
Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC2002), Manchester, UK, April 2002. IEEE Computer Society Press. (PDF)
Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC2003), Vancouver, B.C., Canada, May 2003. IEEE Computer Society Press. (PDF)
Tenth International Symposium on Asynchronous Circuits and Systems (ASYNC2004), Hersonissos, Crete, Greece, April 2004. IEEE Computer Society Press.
R. Auletta, B. Beese, and C. Traver. A comparison of synchronous and asynchronous FSMD designs. In Proc. International Conf. Computer Design (ICCD), pages 178-182, 1993.
O. Aumann and H.-J. Pfleiderer. Design of self-timed pipelined architectures using Petri nets. In Power and Timing Modeling, Optimization and Simulation (PATMOS), October 1995.
U. Baake and S. A. Huss. Logic reduction in timed asynchronous circuits. In Proc. International Symposium on Circuits and Systems, pages 1223-1226, 1995.
Uwe Baake, Markus Ernst, and Sorin A. Huss. An integrated design methodology for asynchronous circuit engineering. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1836-1839, June 1997.
Brandon M. Bachman. Architectural-level synthesis of asynchronous systems. Master's thesis, The University of Utah, December 1998. (PostScript) (PDF)
R.-J. R. Back, A.J. Martin, and K. Sere. An action system specification of the Caltech asynchronous microprocessor. In Third International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science. Springer-Verlag, July 1995.
Rosa M. Badia and Jordi Cortadella. High-level synthesis of asynchronous digital circuits: Scheduling strategies. Technical report, Universitat Politècnica de Catalunya, 1992. (PostScript)
Rosa M. Badia and Jordi Cortadella. High-level synthesis of asynchronous systems: Scheduling and process synchronization. In Proc. European Conference on Design Automation (EDAC), pages 70-74. IEEE Computer Society Press, February 1993.
J. C. M. Baeten and F. W. Vaandrager. Specification and verification of a circuit in ACP (revised version). Report P8821, University of Amsterdam, Programming Research Group, October 1988.
J. C. M. Baeten. Applications of Process Algebra. Cambridge University Press, 1990.
H. T. Bahbouh and A. E. Salama. Synthesis of self-timed fifo circuit from signal transition graphs. In Seventeenth National Radio Science Conference, pages C9/1-C9/8, 2000.
Andrew Bailey and Mark Josephs. Sequencer circuits for VLSI programming. In Asynchronous Design Methodologies, pages 82-90. IEEE Computer Society Press, May 1995.
Andrew Bailey, George A. McCaskill, and George J. Milne. An exercise in the automatic verification of asynchronous designs. Formal Methods in System Design, 4:213-242, 1994.
Andrew Bailey. Automatic verification of speed-independent circuit designs using the circal system. In Correct Hardware Design and Verification Methods (CHARME '93), volume 683 of Lecture Notes in Computer Science, pages 167-178. Springer-Verlag, May 1993.
W. J. Bainbridge and S. B. Furber. Asynchronous macrocell interconnect using MARBLE. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 122-132, 1998.
W. J. Bainbridge and S. B. Furber. MARBLE: An asynchronous on-chip macrocell bus. Microprocessors and Microsystems, 24(4):213-222, April 2000.
W. J. Bainbridge and S. B. Furber. Delay insensitive system-on-chip interconnect using 1-of-4 data encoding. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 118-126. IEEE Computer Society Press, March 2001.
John Bainbridge and Steve Furber. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro, 22:16-23, 2002.
W. J. Bainbridge, W. B. Toms, D. A. Edwards, and S. B. Furber. Delay-insensitive, point-to-point interconnect using M-of-N codes. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 132-140. IEEE Computer Society Press, May 2003.
W. J. Bainbridge, L. A. Plana, and S. Furber. The design and test of a smartcard chip using a CHAIN self-timed network-on-chip. In Design, Automation and Test in Europe -- Designer's Forum, pages 274-279, February 2004.
W. J. Bainbridge. Asynchronous System-on-Chip Interconnect. PhD thesis, Department of Computer Science, University of Manchester, March 2000. (PDF)
John Bainbridge. Asynchronous System-on-Chip Interconnect. Springer-Verlag, 2002.
T. S. Balraj and M. J. Foster. Miss Manners: A specialized silicon compiler for synchronizers. In Charles E. Leierson, editor, Advanced Research in VLSI, pages 3-20. MIT Press, April 1986.
Satish K. Bandapati, Scott C. Smith, and Minsu Choi. Design and charaterization of null convention self-timed multipliers. IEEE Design & Test of Computers, 20(6):26-35, 2003.
S. Banerjee, R. K. Roy, S. T. Chakradhar, and D. J. Pradhan. Circuit initialization issues in asynchronous synthesis. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
S. Banerjee, R. K. Roy, S. T. Chakradhar, and D. K. Pradhan. Signal transition graph transformations for initializability. In Proc. European Conference on Design Automation (EDAC), 1994.
Savita Banerjee, Srimat T. Chakradhar, and Rabindra K. Roy. Synchronous test generation model for asynchronous circuits. In Proc. International Conference on VLSI Design, January 1996.
Savita Banerjee, Rabindra K. Roy, and Srimat T. Chakradhar. Initialization issues in asynchronous circuit synthesis. Journal of Electronic Testing: Theory and Applications, 9(3):237-250, December 1996.
S. Banerjee. New Techniques for Synthesis and Testing of Asynchronous Circuits. PhD thesis, Dept. of Electrical and Computer Engineering, Univ. of Massachusetts Amherst, 1995.
A. Bardsley and D. Edwards. Compiling the language Balsa to delay-insensitive hardware. In C. D. Kloos and E. Cerny, editors, Hardware Description Languages and their Applications (CHDL), pages 89-91, April 1997.
A. Bardsley and D. A. Edwards. The Balsa asynchronous circuit synthesis system. In Forum on Design Languages, September 2000.
A. Bardsley and D. A. Edwards. Synthesising an asynchronous DMA controller with Balsa. Journal of Systems Architecture, 46:1309-1319, 2000.
A. Bardsley. Implementing Balsa Handshake Circuits. PhD thesis, Department of Computer Science, University of Manchester, 2000. (PDF)
H. Barringer, D. Fellows, G. D. Gough, P. Jinks, B. Marsden, and A. Williams. Design and simulation in Rainbow: A framework for asynchronous micropipeline circuits. In A. G. Bruzzone and U. J. H. Kerckhoffs, editors, Proceedings of the European Simulation Symposium, volume 2, pages 567-571. Society for Computer Simulation International, October 1996.
H. Barringer, D. Fellows, G. D. Gough, and A. Williams. Abstract modelling of asynchronous micropipeline systems using Rainbow. In C. D. Kloos and E. Cerny, editors, Hardware Description Languages and their Applications (CHDL), pages 285-304, April 1997.
José C. Barros and Brian W. Johnson. Equivalence of the arbiter, the synchronizer, the latch, and the inertial delay. IEEE Transactions on Computers, 32(7):603-614, July 1983.
V. A. Bartlett and E. Grass. Completion-detection technique for dynamic logic. Electronics Letters, 33(22):1850-1852, 23 Oct 1997.
V. A. Bartlett and E. Grass. A self-timed multiplier using conditional evaluation. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 429-438, October 1998.
V. A. Bartlett and E. Grass. A low-power asynchronous VLSI FIR filter. In Advanced Research in VLSI, pages 29-39, March 2001.
J. Becker, A. Thomas, and M. Scheer. Efficient processor instruction set extension by asynchronous reconfigurable datapath integration. In Proceedings of 16th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 237-242, September 2003.
Marek A. Bednarczyk. Categories of Asynchronous Systems. PhD thesis, University of Sussex, October 1987.
Peter Beerel and Teresa Meng. Semi-modularity and self-diagnostic asynchronous control circuits. In Carlo H. Séquin, editor, Advanced Research in VLSI, pages 103-117. MIT Press, March 1991. (PostScript)
Peter A. Beerel and Teresa H.-Y. Meng. Testability of asynchronous self-timed control circuits with delay assumptions. In Proc. ACM/IEEE Design Automation Conference, pages 446-451. IEEE Computer Society Press, June 1991. (PostScript)
P. Beerel and T.H.-Y. Meng. Automatic gate-level synthesis of speed-independent circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 581-587. IEEE Computer Society Press, November 1992. (PostScript)
P.A. Beerel and T.H.-Y. Meng. Semi-modularity and testability of speed-independent circuits. Integration, the VLSI journal, 13(3):301-322, September 1992. (PostScript)
Peter A. Beerel and Teresa H.-Y. Meng. Gate-level synthesis of speed-independent asynchronous control circuits. In Proceedings of ACM TAU 1992, March 1992. Participant's proceedings.
Peter A. Beerel and Teresa H.-Y. Meng. Logic transformations and observability don't cares in speed-independent circuits. In Proceedings of TAU 1993, September 1993. Participant's proceedings. (PostScript)
Peter A. Beerel and Aiguo Xie. Performance analysis of asynchronous circuits using Markov chains. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 313-344. Springer-Verlag, 2002.
Peter A. Beerel, Teresa H.-Y. Meng, and Jerry Burch. Efficient verification of determinate speed-independent circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 261-267. IEEE Computer Society Press, November 1993. (PostScript)
Peter A. Beerel, Jerry R. Burch, and Teresa H.-Y. Meng. Sufficient conditions for correct gate-level speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 33-43, November 1994. (PostScript)
Peter A. Beerel, Chris J. Myers, and Teresa H.-Y. Meng. Automatic synthesis of gate-level speed-independent circuits. Technical Report CSL-TR-94-648, Stanford University, November 1994.
P. A. Beerel, C.-T. Hsieh, and S. Wadekar. Estimation of energy consumption in speed-independent control circuits. In International Symposium on Low-Power Design, pages 39-44, 1995. (PostScript)
Peter A. Beerel, Kenneth Y. Yun, Steven M. Nowick, and Pei-Chuan Yeh. Estimation and bounding of energy consumption in burst-mode control circuits. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, 1995. (PostScript) (PDF)
P. A. Beerel, K. Y. Yun, and W. C. Chou. Optimizing average-case delay in technology mapping of burst-mode circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. (PostScript) (PDF)
Peter A. Beerel, Wei chun Chou, and Kenneth Y. Yun. A heuristic covering technique for optimizing average-case delay in the technology mapping of asynchronous burst-mode circuits. In Proc. European Design Automation Conference (EURO-DAC), September 1996. (PostScript) (PDF)
P. A. Beerel, J. R. Burch, and T. H.-Y. Meng. Checking combinational equivalence of speed-independent circuits. Formal Methods in System Design, March 1998.
P. A. Beerel, C. J. Myers, and T. H.-Y. Meng. Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Transactions on Computer-Aided Design, March 1998.
Peter A. Beerel, Sangyun Kim, Pei-Chuan Yeh, and Kyeounsoo Kim. Statistically optimized asynchronous barrel shifters for variable length codecs. In International Symposium on Low Power Electronics and Design, pages 261-263, August 1999.
Peter A. Beerel. CAD Tools for the Synthesis, Verification, and Testability of Robust Asynchronous Circuits. PhD thesis, Stanford University, 1994. (PostScript)
Peter A. Beerel. Asynchronous circuits: An increasingly practical design solution. In Proc. of the International Symposium on Quality Electronic Design (ISQED), 2002.
Frank te Beest, Ad Peeters, Kees van Berkel, and Hans Kerkhoff. Synchronous full-scan for asynchronous handshake circuits. In IEEE European Test Workshop (ETW02), pages 381-387, May 2002.
Frank te Beest, Ad Peeters, Marc Verra, Kees van Berkel, and Hans Kerkhoff. Automatic scan insertion and test generation for asynchronous circuits. In Proc. International Test Conference, pages 804-813, October 2002.
Frank te Beest, Ad Peeters, Kees van Berkel, and Hans Kerkhoff. Synchronous full-scan for asynchronous handshake circuits. Journal of Electronic Testing: Theory and Applications, 19:397-406, 2003.
Frank J. te Beest. Full scan testing of handshake circuits. PhD thesis, Twente University, Enschede, The Netherlands, May 2003.
J. Beister and R. Wollowski. Controller implementation by communicating asynchronous sequential circuits from a Petri net specification of required behaviour. In G. Saucier and J. Trilhe, editors, Synthesis of Control Dominated Circuits, pages 103-115. Elsevier Science Publishers, 1993.
J. Beister, M. Kuhn, and R. Wollowski. An asynchronous controller for a daisy-chainable VME bus interrupter. In Third International Workshop on Field Programmable Logic and Applications, 1993.
J. Beister, G. Eckstein, and R. Wollowski. From STG to extended-burst-mode machines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 145-158, April 1999.
J. Beister, G. Eckstein, and R. Wollowski. CASCADE: A tool kernel supporting a comprehensive design method for asynchronous controllers. In Proc. of the International Conference on Application and Theory of Petri Nets, June 2000.
J. Beister. A unified approach to combinational hazards. IEEE Transactions on Computers, C-23(6), 1974.
H. Belhadj, G. Saucier, and M. Yoeli. From trace graphs to modular delay-insensitive circuits. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
J. L. Bell, R. F. Tinder, and M. L. Manwaring. Fast externally asynchronous-internally clocked systems: implementation and analysis of a new genre of self-timed circuits. In Proc. of the Midwest Symposium on Circuits and Systems, volume 1, pages 69-72, 1996.
Wendy Belluomini and Chris J. Myers. Efficient timing analysis algorithms for timed state space exploration. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 88-100. IEEE Computer Society Press, April 1997.
Wendy Belluomini and Chris J. Myers. Timed event-level structures. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, USA, December 1997.
W. Belluomini, C. J. Myers, and H. P. Hofstee. Verification of delayed-reset domino circuits using ATACS. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 3-12, April 1999.
Wendy Belluomini. Algorithms for Synthesis and Verification of Timed Circuits and Systems. PhD thesis, The University of Utah, September 1999. (PostScript) (PDF)
Martin Benes, Andrew Wolfe, and Steven M. Nowick. A high-speed asynchronous decompression circuit for embedded processors. In Advanced Research in VLSI, pages 219-236, September 1997.
M. Benes, S. M. Nowick, and A. Wolfe. A fast asynchronous Huffman decoder for compressed-code embedded processors. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 43-56, 1998.
Igor Benko and Jo Ebergen. Delay-insensitive solutions to the committee problem. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 228-237, November 1994. (PostScript)
Igor Benko and Jo Ebergen. Composing snippets. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 23-33, April 2000.
Igor Benko and Jo Ebergen. Composing snippets. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 1-33. Springer-Verlag, 2002.
Igor Benko. The committee problem and delay-insensitive circuits. Master's thesis, Department of Computer Science, University of Waterloo, May 1993.
Igor Benko. ECF and Asynchronous Circuit Design. PhD thesis, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, 1999. (PostScript) (PDF)
J. A. Bergstra, J. W. Klop, and J. V. Tucker. Process algebra with asynchronous communication mechanisms. In G. Winskel, editor, Seminar on Concurrency, volume 197 of Lecture Notes in Computer Science, pages 76-95. Springer-Verlag, 1985.
Kees van Berkel and Arjan Bink. Single-track handshaking signaling with application to micropipelines and handshake circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 122-133. IEEE Computer Society Press, March 1996.
C. H. (Kees) van Berkel and Charles E. Molnar. Beware the three-way arbiter. IEEE Journal of Solid-State Circuits, 34(6):840-848, June 1999.
Kees van Berkel and Martin Rem. VLSI programming of asynchronous circuits for low power. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 152-210. Springer-Verlag, 1995.
C. H. (Kees) van Berkel and Ronald W. J. J. Saeijs. Compilation of communicating processes into delay-insensitive circuits. In Proc. International Conf. Computer Design (ICCD), pages 157-162. IEEE Computer Society Press, 1988.
C. H. (Kees) van Berkel, Cees Niessen, Martin Rem, and Ronald W. J. J. Saeijs. VLSI programming and silicon compilation. In Proc. International Conf. Computer Design (ICCD), pages 150-166, Rye Brook, New York, 1988. IEEE Computer Society Press.
C. H. (Kees) van Berkel, Martin Rem, and Ronald W. J. J. Saeijs. VLSI programming. In Proc. International Conf. Computer Design (ICCD), pages 152-156. IEEE Computer Society Press, 1988.
Kees van Berkel, Joep Kessels, Marly Roncken, Ronald Saeijs, and Frits Schalij. The VLSI-programming language Tangram and its translation into handshake circuits. In Proc. European Conference on Design Automation (EDAC), pages 384-389, 1991.
Kees van Berkel, Ronan Burgess, Joep Kessels, Marly Roncken, and Frits Schalij. Characterization and evaluation of a compiled asynchronous IC. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 209-221. Elsevier Science Publishers, 1993.
Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, and Frits Schalij. Asynchronous circuits for low power: A DCC error corrector. IEEE Design & Test of Computers, 11(2):22-32, Summer 1994.
Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, and Frits Schalij. A fully-asynchronous low-power error corrector for the DCC player. In International Solid State Circuits Conference, pages 88-89, February 1994.
Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, and Frits Schalij. A fully-asynchronous low-power error corrector for the DCC player. IEEE Journal of Solid-State Circuits, 29(12):1429-1439, December 1994.
Kees van Berkel, Ronan Burgess, Joep Kessels, Ad Peeters, Marly Roncken, Frits Schalij, and Rik van de Wiel. A single-rail re-implementation of a DCC error detector using a generic standard-cell library. In Asynchronous Design Methodologies, pages 72-79. IEEE Computer Society Press, May 1995.
Kees van Berkel, Ferry Huberts, and Ad Peeters. Stretching quasi delay insensitivity by means of extended isochronic forks. In Asynchronous Design Methodologies, pages 99-106. IEEE Computer Society Press, May 1995.
Kees van Berkel, Hans van Gageldonk, Joep Kessels, Cees Niessen, Ad Peeters, Marly Roncken, and Rik van de Wiel. Asynchronous does not imply low power, but .... In Anantha Chandrakasan and Robert Brodersen, editors, Low Power CMOS Design, pages 227-232. IEEE Press, 1998.
C. H. (Kees) van Berkel, Mark B. Josephs, and Steven M. Nowick. Scanning the technology: Applications of asynchronous circuits. Proceedings of the IEEE, 87(2):223-233, February 1999. (PostScript) (PDF)
Kees van Berkel, Ad Peeters, and Frank te Beest. Adding synchronous and LSSD modes to asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 161-170, April 2002. (PDF)
Kees van Berkel, Ad Peeters, and Frank te Beest. Adding synchronous and LSSD modes to asynchronous circuits. Microprocessors and Microsystems, 27(9):461-471, October 2003.
C. H. van Berkel. Beware the isochronic fork. Nat. Lab. Unclassified Report UR 003/91, Philips Research Lab., Eindhoven, The Netherlands, 1991.
Kees van Berkel. Beware the isochronic fork. Integration, the VLSI journal, 13(2):103-128, June 1992.
Kees van Berkel. Handshake Circuits: An Intermediary between Communicating Processes and VLSI. PhD thesis, Eindhoven University of Technology, 1992.
Kees van Berkel. Handshake Circuits: an Asynchronous Architecture for VLSI Programming, volume 5 of International Series on Parallel Computation. Cambridge University Press, 1993.
Kees van Berkel. VLSI programming of a modulo-N counter with constant response time and constant power. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 1-11. Elsevier Science Publishers, 1993.
Kees van Berkel. ESPRIT 6143: Exploitation of asynchronous circuit technologies. In IEEE International Conference on Electronics, Circuits and Systems, pages 764-767, October 1996.
Robert Berks and Jo Ebergen. Response time properties of linear pipelines with varying cell delays. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December 1997.
Robert Berks and Radu Negulescu. Partial-order correctness-preserving properties of delay-insensitive circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 74-83. IEEE Computer Society Press, March 2001.
Robert Berks. Performance Analysis of Asynchronous Networks. PhD thesis, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, July 1998. (PostScript)
Christian Berthet and Eduard Cerny. An algebraic model for asynchronous circuits verification. IEEE Transactions on Computers, 37(7):835-847, July 1988.
Christian Berthet and Eduard Cerny. Synthesis of speed-independent circuits from algebraic specifications. In Proc. International Symposium on Circuits and Systems, volume 2, pages 1869-1872, 1988.
Christian Berthet and Eduard Cerny. Synthesis of speed-independent circuits using set-memory elements. In G. Saucier, editor, Proc. Int'l. Workshop Logic and Arch. Synthesis for Silicon Compilers, Grenoble, France, May 1988.
Christian Berthet and Eduard Cerny. Verification of asynchronous circuits: Behaviors, constraints and specification. In G. Birtwistle and P. A. Subrahmanyam, editors, VLSI Specification, Verification and Synthesis, chapter 13, pages 387-404. Kluwer Academic Publishers, 1988.
Mark Bickford. Composable specifications for asynchronous systems using UNITY. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 216-227, November 1994.
Graham Birtwistle and Al Davis, editors. Asynchronous Digital Circuit Design, Workshops in Computing. Springer-Verlag, 1995.
Graham Birtwistle and Matthew Morley. Specification and property checking of control circuits of TK, an asynchronous AMULET-like processor. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 13-22, July 2000.
Graham Birtwistle. Control states in asynchronous pipelines. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 45-55, July 2000.
Hans Bisseling, Henk Eemers, Michiel Kamps, and Ad Peeters. Designing delay-insensitive circuits. Technical report, IVO, Eindhoven University of Technology, September 1990.
R. J. R. Black, A. J. Martin, and K. Sere. An action system specification of the Caltech asynchronous microprocessor. Science of Computer Programming, 26:79-97, 1996.
David L. Black. On the existence of delay-insensitive fair arbiters: Trace theory and its limitations. Distributed Computing, 1:205-225, 1986.
Robert D. Black. Towards a dynamical systems approach to asynchronous circuit design. Technical report, Dept. of Comp. Sc., Univ. of Waterloo, April 1994.
M. Blaum and J. Bruck. Coding for skew-tolerant parallel asynchronous communications. IEEE Transactions on Information Theory, 39(2):379-388, March 1993.
M. Blaum and J. Bruck. Delay-insensitive pipelined communication on parallel buses. IEEE Transactions on Computers, 44(5):660-668, May 1995.
Ivan Blunno and Luciano Lavagno. Towards a language-based design flow for asynchronous circuits. In Proc. International Workshop on Logic Synthesis, June 1999.
Ivan Blunno and Luciano Lavagno. Automated synthesis of micro-pipelines from behavioral Verilog HDL. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 84-92. IEEE Computer Society Press, April 2000.
I. Blunno, J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou. Handshake protocols for de-synchronization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 149-158. IEEE Computer Society Press, April 2004.
Gregor v. Bochmann. Distributed synchronization and regularity. Computer Networks, 3:36-43, 1979.
Gregor v. Bochmann. Delay-independent design for distributed systems. IEEE Transactions on Software Engineering, SE-14(8):1229-1237, August 1988.
E. Boemo, J. Herrera, and J. Meneses. Logic depth and power consumption in self-timed circuits: A case-study. In Proc. 4th ACiD (Asynchronous Circuit Design) Workshop, Grenoble, February 2000. (PDF)
David S. Bormann and Peter Y.K. Cheung. Asynchronous wrapper for heterogeneous systems. In Proc. International Conf. Computer Design (ICCD), October 1997.
Gaetano Borriello. Synthesis of mixed synchronous/asynchronous control logic. In Proc. International Symposium on Circuits and Systems, volume 2, pages 762-765, 1989.
Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, and Antoine Sirianni. Validation of asynchronous circuit specifications using IF/CADP. In IFIP International Conference on VLSI SoC, December 2003.
H. Boutamine, A. Guyot, B. Elhassan, and M. Renaudin. Asynchronous SRT dividers: The real cost. In Proc. European Design and Test Conference, pages 195-199. IEEE Computer Society Press, March 1996.
L. E. M. Brackenbury, S. B. Furber, and R. Kelly. Transforming architectural models into high performance concurrent implementations. In 1994 UK IT Forum Conference Digest, March 1994. (PostScript)
L. Brackenbury, M. Cumpstey, S. Furber, and P. Riocreux. An asynchronous Viterbi decoder. In Rene van Leuken, Reinder Nouta, and Alexander de Graaf, editors, European Low Power Initiative for Electronic System Design, pages 8-21. Delft Institute of Microelectronics and Submicron Technology, July 2000.
Alex Branover, Rakefet Kol, and Ran Ginosar. Asynchronous design by conversion: Converting synchronous circuits into asynchronous ones. In Proc. Design, Automation and Test in Europe (DATE), pages 870-875, February 2004.
R. W. Brockett. Smooth dynamical systems which realize arithmetical and logical operations. In Hendrik Nijmeijer and Johannes M. Schumacher, editors, Three Decades of Mathematical Systems Theory: A Collection of Surveys at the Occasion of the 50th Birthday of J. C. Willems, volume 135 of Lecture Notes in Control and Information Sciences, pages 19-30. Springer-Verlag, 1989.
Geoffrey Brown, Wayne Luk, and John O'Leary. Retargeting a hardware compiler proof using protocol converters. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 54-63, November 1994.
Geoffrey Brown, Wayne Luk, and John O'Leary. Retargeting a hardware compiler using protocol converters. Formal Aspects of Computing, 8(2):209-237, 1996.
Geoffrey M. Brown. Towards truly delay-insensitive circuit realizations of process algebras. In Geraint Jones and Mary Sheeran, editors, Proceedings of the Workshop on Designing Correct Circuits, pages 120-131. Springer-Verlag, 1990.
Michael C. Browne, Edmund M. Clarke, David L. Dill, and Bud Mishra. Automatic verification of sequential circuits using temporal logic. IEEE Transactions on Computers, 35(12):1035-1044, December 1986.
John Bruna and Stanley M. Altman. A theory of asynchronous control networks. IEEE Transactions on Computers, 20(6):629-638, June 1971.
J. Bruno and S. M. Altman. Asynchronous control networks. In Annual Symposium on Switching and Automata Theory, pages 61-73, 1969.
Erik Brunvand and Robert F. Sproull. Translating concurrent programs into delay-insensitive circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 262-265. IEEE Computer Society Press, November 1989.
E. K. Brunvand and M. Starkey. An integrated environment for the design and simulation of self timed systems. In A. Halaas and P. B. Denyer, editors, VLSI 91, page 4a.2. IFIP, August 1991.
E. Brunvand, M. Michell, and K. Smith. A comparison of self-timed design using FPGA, CMOS, and GaAs technologies. In Proc. International Conf. Computer Design (ICCD), pages 76-80. IEEE Computer Society Press, October 1992.
Erik Brunvand, Steven Nowick, and Kenneth Yun. Practical advances in asynchronous design. In Proc. International Conf. Computer Design (ICCD), pages 662-668, 1997.
Erik Brunvand, Steven Nowick, and Kenneth Yun. Practical advances in asynchronous design and in asynchronous/synchronous interfaces. In Proc. ACM/IEEE Design Automation Conference, pages 104-109, 1999.
Erik Brunvand. Parts-R-Us: A chip aparts... Technical Report CMU-CS-87-119, Carnegie Mellon University, May 1987.
Erik Brunvand. A cell set for self-timed design using Actel FPGAs. Technical Report UUCS-91-013, Dept. of Computer Science, University of Utah, August 1991.
Erik Brunvand. Implementing self-timed systems with FPGAs. In W. R. Moore and W. Luk, editors, FPGAs, pages 312-323. Abingdon EE & CS Books, 1991.
Erik Brunvand. Translating Concurrent Communicating Programs into Asynchronous Circuits. PhD thesis, Carnegie Mellon University, 1991.
Erik Brunvand. The NSR processor. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
Erik Brunvand. Using FPGAs to implement self-timed systems. Journal of VLSI Signal Processing, 6(2):173-190, June 1993.
Erik Brunvand. Designing self-timed systems using concurrent programs. Journal of VLSI Signal Processing, 7(1/2):47-59, February 1994.
Erik Brunvand. Low latency self-timed flow-through FIFOs. In William J. Dally, John W. Poulton, and Alexander T. Ishii, editors, Advanced Research in VLSI, pages 76-90. IEEE Computer Society Press, 1995.
J. A. Brzozowski and J. C. Ebergen. Recent developments in the design of asynchronous circuits. In J. Csirik, J. Demetrovics, and F. Gécseg, editors, Fundamentals of Computation Theory, FCT'89, volume 380 of Lecture Notes in Computer Science, pages 78-94, FCT'89, Szeged, Hungary, 1989. Springer-Verlag.
Janusz A. Brzozowski and Jo C. Ebergen. On the delay-sensitivity of gate networks. IEEE Transactions on Computers, 41(11):1349-1360, November 1992.
J. A. Brzozowski and H. Jurgensen. An algebra of multiple faults in RAMs. Technical report, University of Waterloo, May 1995.
J. A. Brzozowski and R. Negulescu. Automata of asynchronous behaviors. In Proceedings of the 1997 Workshop on Implementing Automata (WIA97), pages 29-45, London, Ontario, Canada, September 1997.
J. A. Brzozowski and R. Negulescu. Automata of asynchronous behaviors. Theoretical Computer Science, 231(1):113-128, January 2000.
J. A. Brzozowski and K. Raahemifar. Testing C-elements is not elementary. In Asynchronous Design Methodologies, pages 150-159. IEEE Computer Society Press, May 1995.
J. A. Brzozowski and C.-J. Seger. A characterization of ternary simulation of gate networks. IEEE Transactions on Computers, C-36(11):1318-1327, November 1987.
J. A. Brzozowski and C.-J. Seger. A unified theory of asynchronous networks. Research Report CS-87-24, Computer Science Dept., Univ. of Waterloo, Cananda, March 1987.
J. A. Brzozowski and C.-J. Seger. A unified framework for race analysis of asynchronous networks. Journal of the ACM, 36(1):20-45, January 1989.
J. A. Brzozowski and C.-J. H. Seger. Advances in asynchronous circuit theory; part I: Gate and unbounded inertial delay models. Bull. EATCS, 42:198-249, October 1990.
J. A. Brzozowski and C.-J. H. Seger. Advances in asynchronous circuit theory; part II: Bounded inertial delay models, MOS circuit design techniques. Bull. EATCS, 43:199-263, February 1991.
Janusz A. Brzozowski and Carl-Johan H. Seger. Asynchronous Circuits. Springer-Verlag, 1995.
J.A. Brzozowski and S. Singh. Definite asynchronous sequential circuits. IEEE Transactions on Computers, C-17(1):18-26, January 1968.
J.A. Brzozowski and M. Yoeli. Practical approach to asynchronous gate networks. Proceedings of the IEE, 123(6):495-498, June 1976.
J.A. Brzozowski and M. Yoeli. On a ternary model of gate networks. IEEE Transactions on Computers, C-28(3):178-184, March 1979.
J. A. Brzozowski and H. Zhang. Delay-insensitivity and semi-modularity. Technical Report CS-97-11, Dept. of Comp. Science, Univ. of Waterloo, March 1997.
J. A. Brzozowski and H. Zhang. Delay-insensitivity and semi-modularity. Formal Methods in System Design, 16(2):187-214, March 2000. (PostScript)
John Brzozowski, Jay Lou, and Radu Negulescu. A characterization of finite ternary algebras. Technical report, University of Waterloo, 1996.
J. A. Brzozowski. Detection of timing problems in VLSI circuits. In Congressus Numerantium, Vol. 56, pages 7-18, 1986. Conference held in Winnipeg, Manitoba, October 1986.
J. A. Brzozowski. Delay-insensitivity and ternary simulation. In Proc. of the First International Conference on Semigroups and Algebraic Engineering. World Scientific Publishing Co. Pte. Ltd., Singapore, March 1997.
J. A. Brzozowski. Delay-insensitivity and ternary simulation. Theoretical Computer Science, 2000. (PostScript)
Wolfgang O. Budde, Hans-Georg Keller, Hans-Jurgen Reumerman, and Paul van de Wiel. An asynchronous, high-speed packet switching component. IEEE Design & Test of Computers, 11(2):33-42, 1994.
Jerry R. Burch. Verifying liveness properties by verifying safety properties. In Robert P. Kurshan and Edmund M. Clarke, editors, Proc. International Workshop on Computer Aided Verification, volume 531 of Lecture Notes in Computer Science, pages 224-232. Springer-Verlag, 1990.
Jerry R. Burch. Delay models for verifying speed-dependent asynchronous circuits. In ACM Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
Jerry R. Burch. Delay models for verifying speed-dependent asynchronous circuits. In Proc. International Conf. Computer Design (ICCD), pages 270-274. IEEE Computer Society Press, October 1992.
R. G. Burford, X. Fan, and N. W. Bergmann. An 180 MHz 16 bit multiplier using asynchronous logic design techniques. In Proc. IEEE Custom Integrated Circuits Conference, pages 215-218, 1994.
Steven M. Burns and Alain J. Martin. Syntax-directed translation of concurrent programs into self-timed circuits. In J. Allen and F. Leighton, editors, Advanced Research in VLSI, pages 35-50. MIT Press, 1988.
Steven M. Burns and Alain J. Martin. Synthesis of self-timed circuits by program transformation. In G. J. Milne, editor, The Fusion of Hardware Design and Verification, pages 99-116. Elsevier Science Publishers, 1988.
Steven M. Burns and Alain J. Martin. Performance analysis and optimization of asynchronous circuits. In Advanced Research in VLSI, pages 71-86. MIT Press, 1991.
Frank Burns, Delong Shang, Albert Koelmans, and Alex Yakovlev. An asynchronous synthesis toolset using verilog. In Proc. Design, Automation and Test in Europe (DATE), pages 724-725, February 2004.
Steven M. Burns. Automated compilation of concurrent programs into self-timed circuits. Master's thesis, California Institute of Technology, 1988.
Steven M. Burns. Performance Analysis and Optimization of Asynchronous Circuits. PhD thesis, California Institute of Technology, 1991.
S. M. Burns. General condition for the decomposition of state holding elements. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
M. E. Bush and M. B. Josephs. Some limitations to speed-independence in asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
Jan Butas, Chiu-Sing Choy, Juraj Povazanec, and Cheong-Fat Chan. Asynchronous cross-pipelined multiplier. IEEE Journal of Solid-State Circuits, 36(8):1272-1275, 2001.
A. Bystrov and A. Yakovlev. Ordered arbiters. Electronics Letters, 35(11):877-879, 1999.
A. Bystrov and A. Yakovlev. Asynchronous circuit synthesis by direct mapping: Interfacing to environment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 127-136, April 2002.
A. Bystrov, D. J. Kinniment, and A. Yakovlev. Priority arbiters. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 128-137. IEEE Computer Society Press, April 2000.
A. Bystrov, D. Sokolov, and A. Yakovlev. Low-latency control structures with slack. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 164-173. IEEE Computer Society Press, May 2003.
J. Calvo, J. I. Acha, and M. Valencia. Asynchronous modular arbiter. IEEE Transactions on Computers, 35(1):67-70, January 1986.
R. Camposano, S. Devadas, K. Keutzer, S. Malik, and A. Wang. Implicit enumeration techniques applied to asynchronous circuit verification. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
G. Cappuccino, G. Cocorullo, P. Corsonello, and S. Perri. High speed self-timed pipelined datapath for square routing. IEE Proceedings, Circuits, Devices and Systems, 146(1):16-22, February 1999.
Luca P. Carloni, Kenneth L. McMillan, Alexandra Saldanha, and Alberto L. Sagiovanni-Vincentelli. A methodology for correct-by-construction latency insensitive design. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 309-315, November 1999.
Josep Carmona, Jordi Cortadella, and Enric Pastor. Synthesis of reactive systems: Application to asynchronous circuit design. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 108-151. Springer-Verlag, 2002.
Gerald Carson and Geatano Borriello. A testable CMOS asynchronous counter. IEEE Journal of Solid-State Circuits, 25(4):952-960, August 1990.
I. Catt. Time loss through gating of asynchronous logic signal pulses. IEEE Transactions on Electronic Computers, EC-15:108-111, February 1966.
Supratik Chakraborty and Rohan Angrish. Probabilistic timing analysis of asynchronous systems with moments of delay. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 99-108, April 2002.
Supratik Chakraborty and David L. Dill. Approximate algorithms for time separation of events. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, 1997.
Supratik Chakraborty and David L. Dill. More accurate polynomial-time mix-max timing simulation. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 112-123. IEEE Computer Society Press, April 1997.
Ajanta Chakraborty and Mark R. Greenstreet. Efficient self-timed interfaces for crossing clock domains. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 78-88. IEEE Computer Society Press, May 2003.
Supratik Chakraborty, David L. Dill, Kenneth Y. Yun, and Kun-Yung Chang. Timing analysis for extended burst-mode circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 101-111. IEEE Computer Society Press, April 1997. (PostScript) (PDF)
Supratik Chakraborty, Kenneth Y. Yun, and David L. Dill. Practical timing analysis of asynchronous systems using time separation of events. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December 1997.
Supratik Chakraborty, Kenneth Y. Yun, and David L. Dill. Practical timing analysis of asynchronous systems using time separation of events. In Proc. IEEE Custom Integrated Circuits Conference, May 1998. (PostScript) (PDF)
Supratik Chakraborty, David L. Dill, and Kenneth Y. Yun. Min-max timing analysis and an application to asynchronous circuits. Proceedings of the IEEE, 87(2):332-346, February 1999. (PostScript) (PDF)
Supratik Chakraborty. Polynomial-Time Techniques for Approximate Timing Analysis of Asynchronous Systems. PhD thesis, Stanford University, August 1998.
S. T. Chakradhar, S. Banerjee, R. K. Roy, and D. K. Pradhan. Synthesis of initializable asynchronous circuits. In Proc. International Conference on VLSI Design, pages 383-388. IEEE Computer Society Press, January 1994.
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, and Dhiraj K. Pradhan. Synthesis of initializable asynchronous circuits. IEEE Transactions on VLSI Systems, 4(2):254-263, June 1996.
V. Chandramouli, Erik Brunvand, and Kent F. Smith. Self-timed design in GaAs---case study of a high-speed, parallel multiplier. IEEE Transactions on VLSI Systems, 4(1):146-149, March 1996.
T. J. Chaney and C. E. Molnar. Anomalous behavior of synchronizer and arbiter circuits. IEEE Transactions on Computers, C-22(4):421-422, April 1973.
Chih-Ming Chang and Shih-Lien Lu. Design of a static MIMD data flow processor using micropipelines. IEEE Transactions on VLSI Systems, 3(3):370-378, September 1995.
Chih-Ming Chang and Shih-Lien Lu. Performance issues on micropipelines. IEEE Technical Committee on Computer Architecture Newsletter, October 1995.
Daniel M. Chapiro. Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, Stanford University, October 1984.
John F. Chappel and Safwat G. Zaky. A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication links. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 156-165, November 1994.
J. F. Chappel and S. G. Zaky. EMI effects and timing design for increased reliability in digital systems. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 44(2):130-142, February 1997.
John F. Chappel. Novel Asynchronous Tools and Techniques. PhD thesis, Dept. of Electrical and Computer Engineering, Univ. of Toronto, 1996.
Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, J.W. Allan, S.P. Klepner, R.V. Joshi, and R.L. Franch. A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE Journal of Solid-State Circuits, 26(11):1577-1585, November 1991.
Tiberiu Chelcea and Steven M. Nowick. Low-latency asynchronous FIFO's using token rings. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 210-220. IEEE Computer Society Press, April 2000.
Tiberiu Chelcea and Steven M. Nowick. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proc. ACM/IEEE Design Automation Conference, June 2001.
Tiberiu Chelcea and Steven M. Nowick. Resynthesis and peephole transformations for the optimization of large-scale asynchronous systems. In Proc. ACM/IEEE Design Automation Conference, June 2002.
Tiberiu Chelcea, Andrew Bardsley, Doug Edwards, and Steven M. Nowick. A burst-mode oriented back-end for the Balsa synthesis system. In Proc. Design, Automation and Test in Europe (DATE), pages 330-337, March 2002.
Wei Chen, Jan Tijmen Udding, and Tom Verhoeff. Networks of communicating processes and their (de)-composition. In Jan L. A. van de Snepscheut, editor, The Mathematics of Program Construction, volume 375 of Lecture Notes in Computer Science, pages 174-196. Springer-Verlag, 1989.
Ren-Der Chen, Jer Min Jou, and Yeu-Horng Shiau. Hazard-free synthesis and decomposition of asynchronous circuits. In Proc. of Asia and South Pacific Design Automation Conference, pages 185-188, 1999.
Fu-Chiung Cheng and Shuen-Long Ho. Efficient systematic error-correcting codes for semi-delay-insensitive data transmission. In Proc. International Conf. Computer Design (ICCD), pages 24-29, November 2001.
F. C. Cheng, S. H. Unger, M. Theobald, and W.-C. Cho. Delay-insensitive carry-lookahead adders. In Proc. International Conference on VLSI Design, pages 322-328, 1997.
F. C. Cheng, S. H. Unger, and M. Theobald. Self-timed carry-lookahead adders. IEEE Transactions on Computers, 49(7):659-672, 2000.
Fu-Chiung Cheng. Synthesis of high speed delay-insensitive combinational iterative tree circuits. In Proc. International Conf. Computer Design (ICCD), pages 301-306, October 1997.
Fu-Chiung Cheng. Practical design and performance evaluation of completion detection circuits. In Proc. International Conf. Computer Design (ICCD), pages 354-359, October 1998.
Jen-Shiun Chiang and Jun-Yao Liao. The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider. In Proc. International Symposium on Circuits and Systems, volume 2, pages 173-176, June 1998.
Jen-Shiun Chiang and Jun-Yao Liao. A novel asynchronous control unit and the application to a pipelined multiplier. In Proc. International Symposium on Circuits and Systems, volume 2, pages 169-172, June 1998.
Jen-Shiun Chiang and Damu Radhakrishnan. Hazard-free design of mixed operating mode asynchronous sequential circuits. Int. Journal Electronics, 68(1):23-37, 1990.
C.-H. Chien and M. A. Franklin. Simulation of asynchronous instruction pipelines. In Proceedings of 1996 Summer Computer Simulation Conference, pages 155-162, 1996.
Chia-Hsing Chien, Mark A. Franklin, Tienyo Pan, and Prithvi Prabhu. ARAS: Asynchronous RISC architecture simulator. In Asynchronous Design Methodologies, pages 210-219. IEEE Computer Society Press, May 1995.
Kyoung-Rok Cho and Kunihiro Asada. VLSI oriented design method of asynchronous sequential circuits based on one-hot state code and two-transistor AND logic. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1793-1796, 1991.
Kyoung-Rok Cho, Kazuma Okura, and Kunihiro Asada. Design of a 32-bit fully asynchronous microprocessor (FAM). In R. W. Newcomb, B. Geller, and M. E. Zaghloul, editors, Proc. of the Midwest Symposium on Circuits and Systems, pages 1500-1503. IEEE Computer Society Press, August 1992.
K. Choi, K. Lee, and J-W. Kang. A self-timed divider using RSD number system. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
Byung-Soo Choi, Dong-Wook Lee, and Dong-Ik Lee. The design of delay insensitive asynchronous 16-bit microprocessor. In Proc. of Asia and South Pacific Design Automation Conference, pages 33-36, 1999.
Kwen-Siong Chong, Bah-Hwee Gwee, and J.S. Chang. Low-voltage asynchronous adders for low power and high speed applications. In Proc. International Symposium on Circuits and Systems, volume 1, pages 873-876, 2002.
Kwen-Siong Chong, Bah-Hwee Gwee, and J.S. Chang. Low-voltage micropower asynchronous multiplier for hearing instruments. In Proc. International Symposium on Circuits and Systems, volume 1, pages 865-868, 2002.
W. Chou, P. A. Beerel, R. Ginosar, R. Kol, C. J. Myers, S. Rotem, K. Stevens, and K. Y. Yun. Average-case optimized technology mapping of one-hot domino circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 80-91, 1998. (PostScript) (PDF)
Wei-Chun Chou, Peter A. Beerel, and Kenneth Y. Yun. Average-case technology mapping of asynchronous burst-mode circuits. IEEE Transactions on Computer-Aided Design, 18(10):1418-1434, October 1999. (PDF)
Per Henrik Christensen, Henrik Hulgaard, and Jørgen Staunstrup. Synthesis of delay insensitive circuits from verified programs. In J.-P. Banatre and D. Le Metayer, editors, Research directions in high-level parallel programming languages, volume 574 of Lecture Notes in Computer Science, pages 326-337. Springer-Verlag, 1992.
K. T. Christensen, P. Jensen, P. Korger, and J. Sparsø. The design of an asynchronous Tiny RISC TR4101 microprocessor core. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 108-119, 1998.
T.-A. Chu and L. A. Glasser. Synthesis of self-timed control circuits form graphs: An example. In Proc. International Conf. Computer Design (ICCD), pages 565-571. IEEE Computer Society Press, 1986.
Tam-Anh Chu and Clement K. C. Leung. Design of VLSI asynchronous FIFO queues for packet communication networks. In Proc. International Conference on Parallel Processing, pages 397-400, August 1986.
Tam-Anh Chu and Narayana S. Mani. CLASS: A CAD system for automatic synthesis and verification of asynchronous finite state machines. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
Tam-Anh Chu and Narayana S. Mani. CLASS: A CAD system for automatic synthesis and verification of asynchronous finite state machines. Integration, the VLSI journal, 15(3):263-289, October 1993.
T.-A. Chu, C. K. C. Leung, and T. S. Wanuga. A design methodology for concurrent VLSI systems. In Proc. International Conf. Computer Design (ICCD), pages 407-410. IEEE Computer Society Press, 1985.
Tam-Anh Chu, Narayana S. Mani, and Clement K. C. Leung. An efficient critical race-free state assignment technique for asynchronous finite state machines. In Proc. ACM/IEEE Design Automation Conference, pages 2-6. IEEE Computer Society Press, June 1993.
Tam-Anh Chu. On the models for designing VLSI asynchronous digital circuits. Integration, the VLSI journal, 4(2):99-113, June 1986.
Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-Theoretic Specifications. PhD thesis, MIT Laboratory for Computer Science, June 1987.
Tam-Anh Chu. Synthesis of self-timed VLSI circuits from graph-theoretic specifications. In Proc. International Conf. Computer Design (ICCD), pages 220-223. IEEE Computer Society Press, 1987.
Tam-Anh Chu. Automatic synthesis and verification of hazard-free control circuits from asynchronous finite state machine specifications. In Proc. International Conf. Computer Design (ICCD), pages 407-413. IEEE Computer Society Press, October 1992.
Tam-Anh Chu. On the specification and synthesis of hazard-free asynchronous control circuits. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1495-1498. IEEE Computer Society Press, 1993.
Tam-Anh Chu. Synthesis of hazard-free control circuits from asynchronous finite state machine specifications. Journal of VLSI Signal Processing, 7(1/2):61-84, February 1994.
H. Y. H. Chuang and S. Das. Synthesis of multiple-input change asynchronous machines using controlled excitation and flip-flops. IEEE Transactions on Computers, C-22(12):1103-1109, December 1973.
Henry Y. H. Chuang and Santanu Das. Multiple-input change asynchronous machines using controlled excitation and flip-flops. In Annual Symposium on Switching and Automata Theory, pages 64-69. IEEE Computer Society Press, 1973.
Y. H. Chuang. Transition logic circuits and a synthesis method. IEEE Transactions on Computers, C-18(2):154-168, February 1969.
S.-H. Chung and S. Furber. The design of the control circuits for an asynchronous instruction prefetch unit using signal transition graphs. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 171-190. Kluwer Academic Publishers, March 2000.
E.C.Y. Chung and L. Kleeman. An optimal approach to implementing self-timed logic circuits from signal transition graphs. Australian Telecommunications Research, 27(2):41-56, 1993.
Edwin C.Y. Chung and Lindsay Kleeman. Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 97-105, November 1994.
G. Ciardo, R. Siminiceanu, and G. Lüttgen. Efficient symbolic state-space construction for asynchronous systems. In Proc. of the International Conference on Application and Theory of Petri Nets, June 2000.
Ian G. Clark and Anthony C. Davies. A comparison of some wait-free communication mechanisms. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 23-31, July 2000.
Wesley A. Clark and Charles E. Molnar. Macromodular computer systems. In Ralph W. Stacy and Bruce D. Waxman, editors, Computers in Biomedical Research, volume IV, chapter 3, pages 45-85. Academic Press, 1974.
I.G. Clark, F. Xia, A.V. Yakovlev, and A.C. Davies. Petri net models of latch metastability. Electronics Letters, 34(7):635-636, April 1998.
Wesley A. Clark. Macromodular computer systems. In AFIPS Conference Proceedings: 1967 Spring Joint Computer Conference, volume 30, pages 335-336, Atlantic City, NJ, 1967. Academic Press.
Mark de Clercq and Radu Negulescu. 1.1-GDI/s transmission between pausible clock domains. In Proc. International Symposium on Circuits and Systems, 2002.
Mark de Clercq. Bridging heterogeneous clock domains using GasP circuits. Master's thesis, Dept. of Electrical and Computer Engineering, McGill University, Montreal, Canada, March 2002.
William S. Coates and Robert J. Drost. Congestion and starvation detection in ripple FIFOs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 36-45. IEEE Computer Society Press, May 2003.
Bill Coates, Al Davis, and Ken Stevens. The Post Office experience: Designing a large asynchronous chip. Integration, the VLSI journal, 15(3):341-366, October 1993.
W. S. Coates, J. K. Lexau, I. W. Jones, S. M. Fairbanks, and I. E. Sutherland. A fifo data switch design experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 4-17, 1998.
Bill Coates, Jo Ebergen, Jon Lexau, Scott Fairbanks, Ian Jones, Alex Ridgway, David Harris, and Ivan Sutherland. A counterflow pipeline experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 161-172, April 1999.
William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, and Ivan E. Sutherland. FLEETzero: An asynchronous switch fabric chip experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 173-182. IEEE Computer Society Press, March 2001.
R. Cockerill, J. Morris, and A. H. J. Sale. Simulation of self-timed integer multipliers. In Proceeding of Microelectronics 1995, pages 180-185, 1995.
J. Compton and A. Albicki. Self-timed pipeline with adder. In Proc. of the Great Lakes Symposium on VLSI, pages 109-113, 1992.
James N. Cook. Production rule verification for quasi-delay-insensitive circuits. Master's thesis, California Institute of Technology, June 1993. (PostScript)
Gianluca Cornetta and Jordi Cortadella. A multi-radix approach to asynchronous division. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 25-34. IEEE Computer Society Press, March 2001.
P. Corsini. Self-synchronizing asynchronous arbiter. Digital Processes, 1:67-73, 1975.
P. Corsini. Speed-independent asynchronous arbiter. IEE journal on Computers and Digital Techniques, 2(5):221-222, October 1979.
P. Corsonello, S. Perri, and G. Cocorullo. VLSI implementation of a low-power high-speed self-timed adder. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 1918 of Lecture Notes in Computer Science, pages 195-204, September 2000.
J. Cortadella and R. M. Badia. An asynchronous architecture model for behavioral synthesis. In Proc. European Conference on Design Automation (EDAC), pages 307-311. IEEE Computer Society Press, 1992.
Jordi Cortadella and Mark Josephs. Proceedings of the 3rd ACiD-WG workshop (on digital signal processing). Technical Report UPC/DAC RR 93/24, Polytechnic University of Catalonia, Barcelona, September 1993.
Jordi Cortadella, Alexandre Yakovlev, Luciano Lavagano, and Peter Vanbekbergen. Designing asynchronous circuits from behavioral specifications with internal conflicts. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 106-115, November 1994. (PostScript)
J. Cortadella, M. Kishinevsky, L. Lavagno, and A. Yakovlev. Synthesizing petri nets from state-based models. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 164-171, 1995.
Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, and Alexandre Yakovlev. Synthesizing Petri nets from state-based models. Technical report, Universitat Politècnica de Catalunya, 1995. (PostScript)
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Complete state encoding based on the theory of regions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. Technical report, Universitat Politècnica de Catalunya, 1996. (PostScript)
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Methodology and tools for state encoding in asynchronous circuit synthesis. In Proc. ACM/IEEE Design Automation Conference, 1996.
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. In XI Conference on Design of Integrated Circuits and Systems, Barcelona, November 1996.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems, E80-D(3):315-325, March 1997. (PostScript)
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, and Alexandre Yakovlev. Decomposition and technology mapping of speed-independent circuits using Boolean relations. In Proc. International Conf. Computer-Aided Design (ICCAD), November 1997.
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alex Yakovlev. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. In Proc. European Design and Test Conference, pages 98-105, 1997.
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. A region-based theory for state assignment in speed-independent circuits. IEEE Transactions on Computer-Aided Design, 16(8):793-812, August 1997.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Taubin, and A. Yakovlev. Lazy transition systems: application to timing optimization of asynchronous circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 324-331, November 1998.
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Alexandre Yakovlev. Automatic handshake expansion and reshuffling using concurrency reduction. In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 86-110, June 1998.
Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, and Alexandre Yakovlev. Deriving Petri nets from finite transition systems. IEEE Transactions on Computers, 47(8):859-882, August 1998.
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, and Ken Stevens. Synthesis of asynchronous control circuits with automatically generated timing assumptions. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 324-331, November 1999.
Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, and Alexandre Yakovlev. Decomposition and technology mapping of speed-independent circuits using Boolean relations. IEEE Transactions on Computer-Aided Design, 18(9), September 1999.
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev. Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.
J. Cortadella, A. Yakovlev, and G. Rozenberg. Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science. Springer-Verlag, 2002.
Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Kenneth S. Stevens, Alexander Taubin, and Alexandre Yakovlev. Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions. IEEE Transactions on Computer-Aided Design, 21(2):109-130, February 2002.
J. Cortadella, A. Kondratyev, L. Lavagno, K. Lwin, and C. Sotiriou. From synchronous to asynchronous: an automatic approach. In Proc. Design, Automation and Test in Europe (DATE), pages 1368-1369, February 2004.
G. R. Couranz and D. F. Wann. Theoretical and experimental behavior of synchronizers operating in the metastable region. IEEE Transactions on Computers, 24(6):604-616, June 1975.
Darren C. Cronquist and Steven M. Burns. Synthesis and analysis of a delay-insensitive folded FIFO, 1995.
Uri Cummings, Andrew Lines, and Alain Martin. An asynchronous pipelined lattice structure filter. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 126-133, November 1994. (PostScript)
William J. Dally and Paul Song. Design of a self-timed VLSI multicomputer communication controller. In Proc. International Conf. Computer Design (ICCD), pages 230-234. IEEE Computer Society Press, 1987.
Andrew Davey and David Lloyd. An evaluation of asynchronous and synchronous design for superscalar architectures. In Proc. International Conf. Computer Design (ICCD), pages 295-300, October 1997.
Ilana David, Ran Ginosar, and Michael Yoeli. An efficient implementation of boolean functions and finite state machines as self-timed circuits. ACM/Sigarch Computer Architecture News, December 1989.
Ilana David, Ran Ginosar, and Michael Yoeli. Self-timed FIFO buffer. Technical Report EE PUB No. 731, Department of Electrical Engineering, Technion, October 1989.
Ilana David, Ran Ginosar, and Michael Yoeli. Self-timed reduced instruction set computer. Technical Report EE PUB No. 732, Department of Electrical Engineering, Technion, October 1989.
Ilana David, Ran Ginosar, and Michael Yoeli. An efficient implementation of boolean functions and finite state machines as self-timed circuits. In International Conference on Computer Systems and Software Engineering (COMP-EURO), pages 148-155. IEEE Computer Society Press, May 1990.
Ilana David, Ran Ginosar, and Michael Yoeli. Self-timed is self-diagnostic. Technical Report EE PUB No. 758, Department of Electrical Engineering, Technion, November 1990.
Ilana David, Ran Ginosar, and Michael Yoeli. An efficient implementation of boolean functions as self-timed circuits. IEEE Transactions on Computers, 41(1):2-11, January 1992.
Ilana David, Ran Ginosar, and Michael Yoeli. Implementing sequential machines as self-timed circuits. IEEE Transactions on Computers, 41(1):12-17, January 1992.
Ilana David, Ran Ginosar, and Michael Yoeli. Self-timed architecture of a reduced instruction set computer. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 29-43. Elsevier Science Publishers, 1993. (PostScript)
Ilana David, Ran Ginosar, and Michael Yoeli. Self-timed is self-checking. Journal of Electronic Testing: Theory and Applications, 6(2):219-228, April 1995.
René David. Modular design of asynchronous circuits defined by graphs. IEEE Transactions on Computers, 26(8):727-737, August 1977.
Rhodri M. Davies and John V. Woods. Timing verification for asynchronous design. In Proc. European Design Automation Conference (EURO-DAC), September 1996.
Al Davis and Steven M. Nowick. Asynchronous circuit design: Motivation, background, and methods. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 1-49. Springer-Verlag, 1995.
Al Davis and Steven M. Nowick. An introduction to asynchronous circuit design. Technical Report UUCS-97-013, Dept. of Computer Science, University of Utah, September 1997. (PostScript) (PDF)
Al Davis and Steven M. Nowick. An introduction to asynchronous circuit design. In A. Kent and J. G. Williams, editors, The Encyclopedia of Computer Science and Technology, volume 38. Marcel Dekker, New York, February 1998.
A. Davis, B. Coates, and K. Stevens. Automatic synthesis of fast compact asynchronous control circuits. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 193-207. Elsevier Science Publishers, 1993.
A. Davis, B. Coates, and K. Stevens. The Post Office experience: Designing a large asynchronous chip. In Proc. Hawaii International Conf. System Sciences, volume I, pages 409-418. IEEE Computer Society Press, January 1993.
Al Davis. Synthesizing asynchronous circuits: Practice and experience. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 104-150. Springer-Verlag, 1995.
Mark Dax. Test quality of asynchronous circuits. Semiconductor International, page 44, January 1997.
Paul Day and J. Viv Woods. Investigation into micropipeline latch design styles. IEEE Transactions on VLSI Systems, 3(2):264-272, June 1995.
Mark Dean, Ted Williams, and David Dill. Efficient self-timing with level-encoded 2-phase dual-rail (LEDR). In Carlo H. Séquin, editor, Advanced Research in VLSI, pages 55-70. MIT Press, 1991.
Mark E. Dean, David L. Dill, and Mark Horowitz. Self-timed logic using current-sensing completion detection (CSCD). In Proc. International Conf. Computer Design (ICCD), pages 187-191. IEEE Computer Society Press, October 1991.
Mark E. Dean, David L. Dill, and Mark Horowitz. Self-timed logic using current-sensing completion detection (CSCD). Journal of VLSI Signal Processing, 7(1/2):7-16, February 1994.
Mark E. Dean. STRiP: A Self-Timed RISC Processor Architecture. PhD thesis, Stanford University, 1992.
Joseph O. Dedou, Daniel Chillet, and Olivier Sentieys. Behavioral synthesis of asynchronous systems: A methodology. In Proc. International Symposium on Circuits and Systems, pages 370-373, 1999.
Z. J. Deng, S. R. Whiteley, and T. Van Duzer. Data-driven self-timing of RSFQ digital integrated circuits. In Extended Abstracts of ISEC 95, pages 189-191, September 1995.
Z. J. Deng, N. Yoshikawa, U. Ghoshal, S. Whiteley, and T. Van Duzer. 20 Gb/s self-timed vector processing with Josephson single-flux quantum technology. In International Solid State Circuits Conference, pages 128-129, 1997.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Asynchronous design methodology for RSFQ digital system. In Extended Abstracts of ISEC 97, July 1997.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Data-driven self-timed RSFQ digital integrated circuit and system. IEEE Transactions on Applied Superconductivity, 7(2):3634-3637, June 1997.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Data-driven self-timed RSFQ digital integrated circuit and system. IEEE Transactions on Applied Superconductivity, 7(2):3634-3637, June 1997.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Data-driven self-timed RSFQ high-speed test system. IEEE Transactions on Applied Superconductivity, 7(4):3830-3833, December 1997.
Z. J. Deng, N. Yoshikawa, J. A. Tiemo, S. R. Whiteley, and T. Van Duzer. Asynchronous circuits and systems in superconducting RSFQ technology. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 274-285, 1998.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Design and testing of data-driven self-timed RSFQ shift register. Applied Superconductivity, 6(10-12):585-589, 1998.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Self-timing and vector processing in RSFQ digital circuit technology. IEEE Transactions on Applied Superconductivity, 9(1):7-17, March 1999.
Z. J. Deng, N. Yoshikawa, S. R. Whiteley, and T. Van Duzer. Simulation and 18 Gb/s testing of a data-driven self-timed RSFQ demultiplexer. IEEE Transactions on Applied Superconductivity, 9(2):4349-4352, June 1999.
Z. John Deng. Self-Timing and Vector-Processing in Superconducting Single Flux Quantum Digital Technology. PhD thesis, University of California, Berkeley, 1997.
Peter J. Denning. The science of computing: The arbitration problem. American Scientist, 73:516-518, December 1985.
J. B. Dennis and S. S. Patil. Speed-independent asynchronous circuits. In Proc. Hawaii International Conf. System Sciences, pages 55-58, 1971.
J. B. Dennis. Modular asynchronous control structures for a high performance processor. In Project MAC Conf. on Concurrent Systems and Parallel Computation, pages 55-80, 1970.
S. Devadas, K. Keutzer, S. Malik, and A. Wang. Verification of asynchronous interface circuits with bounded wire delays. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 188-195. IEEE Computer Society Press, November 1992.
Srinivas Devadas, Kurt Keutzer, Sharad Malik, and Albert Wang. Verification of asynchronous interface circuits with bounded wire delays. Journal of VLSI Signal Processing, 7(1/2):161-182, February 1994.
Stephen P. DeWeerth, Girish N. Patel Dave, E. Schimmel, Mario F. Simoni, and Ronald L. Calabrese. A VLSI architecture for modeling intersegmental coordination. In Advanced Research in VLSI, pages 182-200, September 1997.
Hema Dhanesha and Alexander Albicki. Self-timed adder with pipelined output. In Proc. of the Midwest Symposium on Circuits and Systems, pages 855-858, 1993.
Charles Dike. Advances in metastability theory. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 83-92, July 2000.
David L. Dill and Edmund M. Clarke. Automatic verification of asynchronous circuits using temporal logic. In Henry Fuchs, editor, 1985 Chapel Hill Conference on VLSI, pages 127-143. Computer Science Press, 1985.
David L. Dill and Edmund M. Clarke. Automatic verification of asynchronous circuits using temporal logic. IEE Proceedings, Computers and Digital Techniques, 133:272-282, September 1986.
David L. Dill, Steven M. Nowick, and Robert F. Sproull. Automatic verification of speed-independent circuits with Petri net specifications. In Proc. International Conf. Computer Design (ICCD), pages 212-216. IEEE Computer Society Press, 1989.
David L. Dill, Steven M. Nowick, and Robert F. Sproull. Specification and automatic verification of self-timed queues. Technical Report CSL-TR-89-387, Stanford University, August 1989.
David L. Dill, Steven M. Nowick, and Robert F. Sproull. Specification and automatic verification of self-timed queues. Formal Methods in System Design, 1(1):29-60, July 1992.
David L. Dill. Trace theory for automatic hierarchical verification of speed-independent circuits. In Jonathan Allen and F. Thomson Leighton, editors, Advanced Research in VLSI, pages 51-65. MIT Press, 1988.
David L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. ACM Distinguished Dissertations. MIT Press, 1989.
R. Dobkin, R. Ginosar, and C. P. Sotiriou. Data synchronization issues in GALS SoCs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 170-179. IEEE Computer Society Press, April 2004.
D. Donaghy, L. Brackenbury, and S. Hall. Exploiting asynchronous self-timed techniques on SOI technology for low power. In EUROSOI 2000 Workshop, Granada, pages 1-4, October 2000.
Jo Ebergen and Robert Berks. VERDECT: A verifier for asynchronous circuits. IEEE Technical Committee on Computer Architecture Newsletter, October 1995. (PostScript)
Jo Ebergen and Robert Berks. Response time properties of some asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 76-86. IEEE Computer Society Press, April 1997.
Jo Ebergen and Robert Berks. Response time properties of linear asynchronous pipelines. Proceedings of the IEEE, 87(2):308-318, February 1999.
Jo Ebergen and Sylvain Gingras. A verifier for network decompositions of command-based specifications. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
Jo C. Ebergen and Sylvain Gingras. An asynchronous stack with constant response time. Technical Report CS-93-11, Computer Science Dept., Univ. of Waterloo, Canada, January 1993.
Jo C. Ebergen and Ad M. G. Peeters. Modulo-N counters: Design and analysis of delay-insensitive circuits. In Jørgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 27-46. Elsevier Science Publishers, 1992.
Jo C. Ebergen and Ad M. G. Peeters. Design and analysis of delay-insensitive modulo-N counters. Formal Methods in System Design, 3(3):211-232, December 1993.
J. C. Ebergen, P. F. Bertrand, and S. Gingras. Solving a mutual exclusion problem with the rgd arbiter. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 137-147. Elsevier Science Publishers, 1993.
Jo C. Ebergen, John Segers, and Igor Benko. Parallel program and asynchronous circuit design. Technical Report CS-94-10, Computer Science Dept., Univ. of Waterloo, Canada, March 1994.
Jo C. Ebergen, John Segers, and Igor Benko. Parallel program and asynchronous circuit design. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 51-103. Springer-Verlag, 1995.
J. C. Ebergen, S. Fairbanks, and I. E. Sutherland. Predicting performance of micropipelines using Charlie diagrams. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 238-246, 1998.
J. Ebergen, D. Finchelstein, R. Kao, J. Lexau, and D. Hopkins. A fast and energy-efficient stack. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 7-16. IEEE Computer Society Press, April 2004.
J. Ebergen, J. Gainsley, and P. Cunningham. Transistor sizing: How to control the speed and energy consumption of a circuit. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 51-61. IEEE Computer Society Press, April 2004.
Jo C. Ebergen. Translating Programs into Delay-Insensitive Circuits. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1987.
Jo C. Ebergen. From functional specification to a delay-insensitive circuit. Technical Report CS-89-44, University of Waterloo, October 1989.
Jo C. Ebergen. Translating Programs into Delay-Insensitive Circuits, volume 56 of CWI Tract. Centre for Mathematics and Computer Science, 1989.
Jo C. Ebergen. Arbiters: An exercise in specifying and decomposing asynchronously communicating components. Research Report CS-90-29, Computer Science Dept., Univ. of Waterloo, Canada, July 1990.
Jo C. Ebergen. A formal approach to designing delay-insensitive circuits. Distributed Computing, 5(3):107-119, 1991.
Jo C. Ebergen. Parallel computations and delay-insensitive circuits. In Graham Birtwistle, editor, IV Higher Order Workshop, Banff 1990, pages 85-104. Springer-Verlag, 1991.
Jo C. Ebergen. Arbiters: an exercise in specifying and decomposing asynchronously communicating components. Science of Computer Programming, 18(3):223-245, June 1992.
Jo Ebergen. Squaring the FIFO in GasP. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 194-205. IEEE Computer Society Press, March 2001.
Doug Edwards and Andrew Bardsley. Balsa: An asynchronous hardware synthesis language. The Computer Journal, 45(1):12-18, 2002.
Aristides Efthymiou and Jim D. Garside. Adaptive pipeline structures fo speculation control. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46-55. IEEE Computer Society Press, May 2003.
A. Efthymiou, J. D. Garside, and S. Temple. A comparative power analysis of an asynchronous processor. In Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 10.1.1-10, September 2001. (PDF)
A. Efthymiou, W. Suntiamorntut, J. Garside, and L. Brackenbury. An asynchronous, iterative implementation of the original Booth multiplication algorithm. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 207-215. IEEE Computer Society Press, April 2004.
Aristides Efthymiou, Christos Sotiriou, and Douglas Edwards. Automatic scan insertion and pattern generation for asynchronous circuits. In Proc. Design, Automation and Test in Europe (DATE), pages 672-673, February 2004.
E. B. Eichelberger. Hazard detection in combinational and sequential switching circuits. IBM Journal of Research and Development, 9:90-99, March 1965.
Kent L. Einspahr and Sharad C. Seth. A switch-level test generation system for synchronous and asynchronous circuits. Journal of Electronic Testing: Theory and Applications, 6(1):59-73, February 1995.
W. Eisele, G. Eckstein, and J. Beister. VMEbus controller synthesis by communicating asynchronous sequential circuits. In IFIP Workshop on Logic and Architecture Synthesis, pages 261-265, December 1994.
W. Eisele. Mirror procedure for one-shot-coding of finite state machines. In Proceedings of the 4th International Workshop on Boolean Problems, pages 159-166, September 2000. (PDF)
W. Eisele. Zustandscodierung sequentieller Schaltungen mit einschrittigen, wettlauffreien Codes. Shaker Verlag, Aachen, Germany, April 2000. ISBN 3-8265-7273-4; In German.
Virantha N. Ekanayak and Rajit Manohar. Asynchronous DRAM design and synthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 174-183. IEEE Computer Society Press, May 2003.
C. J. Elston, D. B. Christianson, P. A. Findlay, and G. B. Steven. Hades - towards the design of an asynchronous superscalar processor. In Asynchronous Design Methodologies, pages 200-209. IEEE Computer Society Press, May 1995.
K. Emerson. Asynchronous design--an interesting alternative. In Proc. International Conference on VLSI Design, pages 318-320, January 1997.
Philip Endecott and Stephen Furber. Behavioural modelling of asynchronous systems for power and performance analysis. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 137-146, October 1998.
P. B. Endecott. Processor architectures for power efficiency and asynchronous implementation. Master's thesis, Department of Computer Science, University of Manchester, 1993. (PostScript)
Philip B. Endecott. Parallel structures for asynchronous microprocessors. IEEE Technical Committee on Computer Architecture Newsletter, October 1995. (PostScript)
P. B. Endecott. SCALP: A Superscalar Asynchronous Low-Power Processor. PhD thesis, Department of Computer Science, University of Manchester, 1996. (PostScript) (PDF)
P. B. Endecott. Superscalar instruction issue in an asynchronous microprocessor. IEE Proceedings, Computers and Digital Techniques, 143(5):266-272, September 1996.
W. Erhard, A. Reinsch, and T. Schober. First steps towards a reconfigurable asynchronous system. In IEEE International Workshop on Rapid System Prototyping, pages 28-31, June 1999.
J. Escriba and J. A. Carrasco. Self-timed Manchester chain carry propagate adder. Electronics Letters, 32(8):708-710, 1996.
K. Eshraghian, J. A. Montiel-Nelson, and S. Nooshabadi. An asynchronous morphological processor for multi-media applications. In Proc. International Conference on VLSI Design, pages 336-341, January 1997.
Scott Fairbanks and Simon Moore. Analog micropipeline rings for high precision timing. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 41-50. IEEE Computer Society Press, April 2004.
Xingcha Fan and Neil Bergmann. Design of elements for a self-timed fast packet switch. In Proc. International Symposium on Circuits and Systems, volume 2, pages 1025-1028, 1991.
Xingcha Fan and Neil Bergmann. Architecture design of a fully asynchronous VLSI chip for DSP custom applications. In Proc. International Symposium on Circuits and Systems, volume 5, pages 2112-2115, 1992.
D. Fang and R. Manohar. Non-uniform access asynchronous register files. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 75-85. IEEE Computer Society Press, April 2004.
Ting-Pien Fang and Charles E. Molnar. Synthesis of reliable speed-independent circuit modules: II. circuit and delay conditions to ensure operation free of problems from races and hazards. Technical Memorandum 298, Computer Systems Laboratory, Institute for Biomedical Computing, Washington Univ., St. Louis, MO, 1983.
Ting-Pien Fang. An extension of Q-module realization. Technical Memorandum 317, Computer Systems Laboratory, Washington Univ., St. Louis, MO, November 1986.
Ting-Pien Fang. On decomposition of delay-insensitive modules by factoring. Technical Memorandum 314, Computer Systems Laboratory, Washington Univ., St. Louis, MO, July 1986.
Karl M. Fant and Scott A. Brandt. NULL conventional logic: A complete and consistent logic for asynchronous digital circuit synthesis. In International Conference on Application-specific Systems, Architectures, and Processors, pages 261-273, 1996.
Craig Farnsworth, Doug Edwards, and Shiv Sikand. Utilizing dynamic logic for low power consumption in asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 186-194, November 1994. (PostScript)
C. Farnsworth, P. Day, D. A. Edwards, S. V. Morton, S. S. Appleton, and M. J. Liebelt. Asynchronous pipelining techniques and applications. In Proceeding of Microelectronics 1995, pages 86-90, July 1995.
C. Farnsworth, D. A. Edwards, Jianwei Liu, and S. S. Sikand. A hybrid asynchronous system design environment. In Asynchronous Design Methodologies, pages 91-98. IEEE Computer Society Press, May 1995.
Tomaz Felicijan and Steve B. Furber. An asynchronous ternary logic signaling system. IEEE Transactions on VLSI Systems, 20(6):1114-1119, 2003.
Marcos Ferretti and Peter A. Beerel. Single-track asynchronous pipeline templates using 1-of-N encoding. In Proc. Design, Automation and Test in Europe (DATE), pages 1008-1015, March 2002.
M. Ferretti, R. Ozdag, and P. Beerel. High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 95-105. IEEE Computer Society Press, April 2004.
Christof Fetzer. Perfect failure detection in timed asynchronous systems. IEEE Transactions on Computers, 52(2):99-112, February 2003.
P. David Fisher and Sheng-Fu Wu. Race-free state assignments for synthesizing large-scale asynchronous sequential logic circuits. IEEE Transactions on Computers, 42(9):1025-1034, September 1993.
W. Fleischhammer and O. Dortok. The anomalous behavior of flip-flops in synchronizer circuits. IEEE Transactions on Computers, 28(3):273-276, March 1979. Comments: see Lacroix 1982.
J. Fragoso, G. Sicard, and M. Renaudin. Automatic generation of 1-of-M QDI asynchronous adders. In Proceedings of 16th Symposium on Integrated Circuits and Systems Design (SBCCI), pages 149-154, September 2003.
João Loenardo Fragoso, Gilles Sicard, and Marc Renaudin. Power/area tradeoffs in 1-of-M parallel-prefix asynchronous adders. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 171-180, September 2003.
Felipe M. G. França, Vladimir C. Alves, and Edson P. Granja. Edge reversal-based asynchronous timing synthesis. In Proc. International Symposium on Circuits and Systems, pages 45-48, June 1998.
Edward H. Frank and Robert F. Sproull. A self-timed static RAM. In Randal Bryant, editor, Proceedings of Third Caltech Conference on VLSI, pages 275-285. Computer Science Press, 1983.
Mark A. Franklin and Tienyo Pan. Clocked and asynchronous instruction pipelines. In Proc. 26th ACM/IEEE Symp. on Microarchitecture, pages 177-184, Austin, TX, December 1993.
Mark A. Franklin and Tienyo Pan. Performance comparison of asynchronous adders. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 117-125, November 1994.
M. A. Franklin and P. Prabhu. Performance optimization of self-timed circuits. In Proc. of the Great Lakes Symposium on VLSI, pages 374-379, 1998.
M. A. Franklin and D. F. Wann. Asynchronous and clocked control structures for VLSI based interconnection networks. In Proceedings IEEE Symposium on Computer Architecture, pages 50-59, April 1982.
M. A. Franklin, D. Wann, and S. Dhar. Regular array processors: Asynchronous versus clocked control. In Proceedings 1983 Conf. on Information Science and Systems, pages 724-732, 1983.
A. D. Friedman and P. R. Menon. Synthesis of asynchronous sequential circuits with multiple-input changes. IEEE Transactions on Computers, C-17(6):559-566, June 1968.
A. D. Friedman and P. R. Menon. Systems of asynchronously operating modules. IEEE Transactions on Computers, 20:100-104, 1971.
A. D. Friedman, R. L. Graham, and J. D. Ullman. Universal single transition time asynchronous state assignments. IEEE Transactions on Computers, C-18:541-547, June 1969.
G. Frosini and G. B. Gerace. Synthesis of asynchronous sequential circuits with master-slave subcircuits. In Annual Symposium on Switching and Automata Theory, pages 60-78. IEEE Computer Society Press, 1971.
Robert M. Fuhrer and Steven M. Nowick. OPTIMISTA: State minimization of asynchronous FSMs for optimum output logic. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 7-13. IEEE Computer Society Press, November 1999.
Robert M. Fuhrer and Steven M. Nowick. Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools. Kluwer Academic Publishers, 2001.
Robert M. Fuhrer, Bill Lin, and Steven M. Nowick. Symbolic hazard-free minimization and encoding of asynchronous finite state machines. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, 1995.
R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin, and L. Plana. Minimalist: An environment for the synthesis, verification and testability of burst-mode asynchronous machines. Technical Report TR CUCS-020-99, Columbia University, NY, July 1999.
Robert M. Fuhrer. Sequential optimization of asynchronous and synchronous finite-state machines. PhD thesis, Columbia University, NY, 1999.
Stephen B. Furber and Paul Day. Four-phase micropipeline latch control circuits. IEEE Transactions on VLSI Systems, 4(2):247-253, June 1996. (PostScript)
S. Furber and M. Edwards, editors. IFIP Working Conference on Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, Manchester, UK, 1993. Elsevier Science Publishers.
S. B. Furber and J. Liu. Dynamic logic in four-phase micropipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
S. B. Furber and A. V. Yakovlev, editors. Proceedings of the Second UK Asynchronous Forum, 1997.
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods. A micropipelined ARM. In T. Yanagawa and P. A. Ivey, editors, Proceedings of VLSI 93, pages 5.4.1-5.4.10, September 1993. (PostScript)
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, S. Temple, and J. V. Woods. The design and evaluation of an asynchronous microprocessor. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994. (PostScript)
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods. AMULET1: A micropipelined ARM. In Proceedings IEEE Computer Conference (COMPCON), pages 476-485, March 1994. (PostScript)
S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and S. Temple. AMULET2e. In C. Muller-Schloer, F. Geerinckx, B. Stanford-Smith, and R. van Riet, editors, Embedded Microprocessor Systems, September 1996. Proceedings of EMSYS'96 - OMI Sixth Annual Conference. (PostScript)
S. B. Furber, J. D. Garside, S. Temple, J. Liu, P. Day, and N. C. Paver. AMULET2e: An asynchronous embedded controller. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 290-299. IEEE Computer Society Press, April 1997.
S. B. Furber, J. D. Garside, and S. Temple. Power-saving features in Amulet2e. In Power Driven Microarchitecture Workshop, June 1998.
Stephen B. Furber, James D. Garside, and David A. Gilbert. AMULET3: A high-performance self-timed ARM microprocessor. In Proc. International Conf. Computer Design (ICCD), October 1998. (PostScript)
Stephen B. Furber, James D. Garside, Peter Riocreux, Steven Temple, Paul Day, Jianwei Liu, and Nigel C. Paver. AMULET2e: An asynchronous embedded controller. Proceedings of the IEEE, 87(2):243-256, February 1999.
S. B. Furber, D. A. Edwards, and J. D. Garside. AMULET3: a 100 MIPS asynchronous embedded processor. In Proc. International Conf. Computer Design (ICCD), September 2000. (PostScript)
S. B. Furber, A. Efthymiou, and Montek Singh. A power-efficient duplex communication system. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 145-150, July 2000.
Steve B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, and Steve Temple. Power management in the Amulet microprocessors. IEEE Design & Test of Computers, 18(2):42-52, 2001.
S. B. Furber. Breaking step: the return of asynchronous logic. IEE Review, 39(4):159-162, July 1993. (PostScript)
S. Furber. Computing without clocks: Micropipelining the ARM processor. In Graham Birtwistle and Al Davis, editors, Asynchronous Digital Circuit Design, Workshops in Computing, pages 211-262. Springer-Verlag, 1995.
S. B. Furber. Real-time without clocks? Real-Time Magazine, 96/4:88-91, 1996.
S. B. Furber. Asynchronous design. In W. Nebel and J. Mermet, editors, Proceedings of Submicron Electronics, Il Ciocco, Italy, 20-30 Aug. 1996, pages 461-492, 1997.
S. B. Furber. Kicking out the clock. Integrated System Design, 12(129):30-38, May 2000.
Steve B. Furber. Validating the amulet microprocessors. The Computer Journal, 45(1):19-26, 2002.
D. Furey and M. B. Josephs. Delay insensitive interface specification. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 75-80, July 2000.
Hans van Gageldonk, Daniel Baumann, Kees van Berkel, Daniel Gloor, Ad Peeters, and Gerhard Stegmann. An asynchronous low-power 80c51 microcontroller. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 96-107, 1998.
Hans van Gageldonk. The asynchronous move machine: Verification using CCS. Master's thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, August 1994.
Hans van Gageldonk. VLSI-programming of low-power applications. In Proc. of the IEEE/ProRISC Symposium on Circuits, Systems and Signal Processing, 1996.
Hans van Gageldonk. An Asynchronous Low-Power 80C51 Microcontroller. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, September 1998.
K. Gaj, E. G. Friedman, and M. J. Feldman. Timing of multi-gigahertz rapid single flux quantum digital circuits. Journal of VLSI Signal Processing, 16(2-3):247-276, 1997.
Mike J. Gamble. A novel current-sensing completion-detection circuit adapted to the micropipeline methodology. Master's thesis, University of Manitoba, Canada, 1994.
Anders Gammelgaard. Implementation conditions for delay-insensitive circuits. In E. Odijk, M. Rem, and J.-C. Syre, editors, PARLE '89: Parallel Architectures and Languages Europe, volume 365 of Lecture Notes in Computer Science, pages 341-355. Springer-Verlag, 1989.
T. A. Garcia, A. J. Acosta, J. M. Mora, J. M. Ramos, and J. L. Huertas. Self-timed boundary-scan cells for multi-chip module test. In Proc. IEEE VLSI Test Symposium, April 1998.
O. Garnica, J. Lanchares, and R. Hermida. A new methodology to design low-power asynchronous circuits. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2451 of Lecture Notes in Computer Science, September 2002.
Jim Garside. The Asynchronous Logic Homepage. http://www.cs.man.ac.uk/amulet/async/.
J. D. Garside, S. Temple, and R. Mehra. The AMULET2e cache system. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. (PostScript)
J. D. Garside, S. B. Furber, and S.-H. Chung. AMULET3 revealed. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 51-59, April 1999.
J. D. Garside, W. J. Bainbridge, A. Bardsley, D. A. Edwards, S. B. Furber, J. Liu, D. W. Lloyd, S. Mohammadi, J. S. Pepper, O. Petlin, S. Temple, and J. V. Woods. AMULET3i --- an asynchronous system-on-chip. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 162-175. IEEE Computer Society Press, April 2000. (PDF)
Jim D. Garside. A CMOS VLSI implementation of an asynchronous ALU. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 181-207. Elsevier Science Publishers, 1993. (PostScript)
W. Wayt Gibbs. Turning back the clock. Scientific American, 272(6), June 1995.
D. A. Gilbert and J. D. Garside. A result forwarding mechanism for asynchronous pipelined systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2-11. IEEE Computer Society Press, April 1997.
David Alan Gilbert. Dependency and Exception Handling in an Asynchronous Microprocessor. PhD thesis, Department of Computer Science, University of Manchester, 1997. (PDF)
Bruce Gilchrist, J. H. Pomerene, and S. Y. Wong. Fast carry logic for digital computers. IRE Transactions on Electronic Computers, EC-4(4):133-136, December 1955.
Ran Ginosar and Rakefet Kol. Adaptive synchronization. In Proc. International Conf. Computer Design (ICCD), pages 188-189, October 1998.
Ran Ginosar and Rakefet Kol. Adaptive synchronization. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 93-101, July 2000.
Ran Ginosar. Fourteen ways to fool your synchronizer. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 89-96. IEEE Computer Society Press, May 2003.
A. Ginzburg and M. Yoeli. Synthesis of delay-insensitive circuits specified by trace graphs. Technical Report 663, Dept. Comp. Science, Technion, Haifa, Israel, 1991.
Alessandro De Gloria and Mauro Olivieri. Efficient semicustom micropipeline design. IEEE Transactions on VLSI Systems, 3(3):464-469, September 1995.
Alessandro De Gloria and Mauro Olivieri. Statistical carry lookahead adders. IEEE Transactions on Computers, 45(3):340-347, March 1996.
A. De Gloria and M. Olivieri. Completion-detecting carry select addition. IEE Proceedings, Computers and Digital Techniques, 147(2):93-100, 2000.
A. De Gloria and M. Olivieriand P. Palma. Delay-insensitive synthesis of the MCS 251 microcontroller core for low power applications. In Proceedings of the 25th EUROMICRO Conference, pages 244-247, 1999.
A. De Gloria, P. Faraboschi, and M. Olivieri. A delay-insensitive approach to the VLSI design of a DRAM controller. In EUROMICRO 92, September 1992.
A. De Gloria, P. Faraboschi, and M. Olivieri. Delay-insensitive micropipelined combinational logic. Microproc. & Microprog., Euromicro Journal, 36:225-241, October 1993.
Alessandro De Gloria, Paolo Faraboschi, and Mauro Olivieri. Design and characterization of a standard cell set for delay insensitive VLSI design. IEEE Transactions on Circuits and Systems, II: Analog and Digital Signal Processing, 41(6):410-415, June 1994.
D. M. Goldschlag. Mechanically verifying safety and liveness properties of delay insensitive circuits. In K. G. Larsen and A. Skou, editors, Proc. International Workshop on Computer Aided Verification, volume 575 of Lecture Notes in Computer Science, pages 354-364. Springer-Verlag, 1991.
Rodney M. Goodman and Anthony J. McAuley. An efficient asynchronous multiplier. In K. Bromley, S.-Y. Kung, and E. Swartzlander, editors, Proceedings of the Second International Conference on Systolic Arrays, pages 593-599. IEEE Computer Society Press, May 1988.
Rodney M. Goodman, Kathleen A. Kramer, and Anthony J. McAuley. Exploiting the inherent fault tolerance of asynchronous arrays. In J. McCanny, J. McWhirter, and E. Swartzlander, editors, Systolic Array Processors, pages 567-576. Prentice-Hall, May 1989. Proceedings of the International Conference on Systolic Arrays.
Gert Goossens and Mark B. Josephs. Proceedings of ACiD-WG/EXACT workshop on asynchronous controllers and interfaces. Technical Report EXACT/D.2/IMEC/m3/D1, IMEC, Leuven, Belgium, September 1992.
G. Gopalakrishnan and V. Akella. VLSI asynchronous systems: Specification and synthesis. Microprocessors and Microsystems, 16(10):517-527, 1992.
G. Gopalakrishnan and V. Akella. Specification, simulation, and synthesis of self-timed circuits. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
G. Gopalakrishnan and V. Akella. A transformational approach to asynchronous high-level synthesis. In T. Yanagawa and P. A. Ivey, editors, Proceedings of VLSI 93, pages 5.3.1-5.3.10, September 1993.
Ganesh Gopalakrishnan and Venkatesh Akella. High level optimizations in compiling process descriptions to asynchronous circuits. Journal of VLSI Signal Processing, 7(1/2):33-45, February 1994.
Ganesh Gopalakrishnan and Prabhat Jain. Some recent asynchronous system design methodologies. Technical Report UUCS-TR-90-016, Dept. of Computer Science, University of Utah, October 1990.
Suresh K. Gopalakrishnan and Gary K. Maki. VLSI asynchronous sequential circuit design. In Proc. International Conf. Computer Design (ICCD), pages 238-242. IEEE Computer Society Press, September 1990.
G. Gopalakrishnan, P. Kudva, and E. Brunvand. Peephole optimization of asynchronous macromodule networks. In Proc. International Conf. Computer Design (ICCD), pages 442-446. IEEE Computer Society Press, October 1994.
Ganesh Gopalakrishnan, Erik Brunvand, Nick Michell, and Steven Nowick. A correctness criterion for asynchronous circuit validation and optimization. IEEE Transactions on Computer-Aided Design, 13(11):1309-1318, November 1994.
Ganesh Gopalakrishnan, Prabhakar Kudva, and Erik Brunvand. Peephole optimization of asynchronous macromodule networks. IEEE Transactions on VLSI Systems, 7(1):30-37, March 1999.
Ganesh Gopalakrishnan. Some unusual micropipeline circuits. Technical Report UUCS-93-015, Dept. of Computer Science, University of Utah, July 1993.
Ganesh Gopalakrishnan. Developing micropipeline wavefront arbiters. IEEE Design & Test of Computers, 11(4):55-64, Winter 1994.
E. Grass and S. Jones. Asynchronous circuits based on multiple localised current-sensing completion detection. In Asynchronous Design Methodologies, pages 170-177. IEEE Computer Society Press, May 1995.
E. Grass and S. Jones. Activity monitoring completion detection (AMCD): A new approach to achieve self-timing. Electronics Letters, 32(2):86-88, 1996.
Eckhard Grass and Frank Winkler. Datenfluss pur - datengetriebener medianfilter als ungetakteter LCA-schaltkreis. Elektronik, 43(1):68-75, 1994. Purely data-flow - Implementation of a self-timed median filter in a XILINX FPGA.
E. Grass, R. C. S. Morling, and I. Kale. Activity monitoring completion detection (AMCD): A new single rail approach to achieve self-timing. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
E. Grass, V. Bartlett, and I. Kale. Completion-detection techniques for asynchronous circuits. IEICE Transactions on Information and Systems, E80-D(3):344-350, March 1997.
Eckhard Grass, Bodhisatya Sarker, and Koushik Maharatna. A dual-mode synchronous/asynchronous CORDIC processor. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 76-83, April 2002.
Frank Grassert and Dirk Timmermann. Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs. In Proc. International Symposium on Circuits and Systems, volume 4, pages 144-147, 2001.
Mark R. Greenstreet and Peter Cahoon. How fast will the flip flop? In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 77-86, November 1994.
Mark R. Greenstreet and Brian de Alwis. How to achieve worst-case performance. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 206-216. IEEE Computer Society Press, March 2001.
Mark Greenstreet and Tarik Ono-Tesfaye. A fast, asP*, RGD arbiter. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 173-185, April 1999.
Mark R. Greenstreet and Kenneth Steiglitz. Bubbles can make self-timed pipelines fast. Journal of VLSI Signal Processing, 2(3):139-148, November 1990.
M. R. Greenstreet, T. E. Williams, and J. Staunstrup. Self-timed iteration. In Carlo H. Séquin, editor, VLSI '87. VLSI Design of Digital Systems, pages 309-322. North-Holland, August 1987.
Mark R. Greenstreet. Implementing a STARI chip. In Proc. International Conf. Computer Design (ICCD), pages 38-43. IEEE Computer Society Press, 1995.
M. R. Greenstreet. Real-time merging. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 186-198, April 1999.
Jerry L. Greer. A self-timed circuit for halftone generation. Master's thesis, Dept. of Electrical Engineering, University of South Alabama, December 1995.
Rix Groenboom, Mark B. Josephs, Paul G. Lucassen, and Jan Tijmen Udding. Normal form in a delay-insensitive algebra. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 57-70. Elsevier Science Publishers, 1993.
Jun Gu and Ruchir Puri. Asynchronous circuit synthesis with boolean satisfiability. IEEE Transactions on Computer-Aided Design, 14(8):961-973, August 1995.
Frank Gürkaynak, Thomas Villiger, Stephan Oetiker, Norbert Felber, Hubert Kaeslin, and Wolfgang Fichtner. A functional test methodology for globally-asynchronous locally-synchronous systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 181-189, April 2002. (PDF)
Dong Sam Ha and Sudhaker M. Reddy. On testable self-timed logic circuits. In Proc. International Conf. Computer Design (ICCD), pages 296-301. IEEE Computer Society Press, 1984.
Jaco Haans, Kees van Berkel, Ad Peeters, and Frits Schalij. Asynchronous multipliers as combinational handshake circuits. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 149-163. Elsevier Science Publishers, 1993.
K. Hamaguchi, H. Hiraishi, and S. Yajima. Formal verification of speed-dependent asynchronous circuits using symbolic model checking of branching time regular temporal logic. In K. G. Larsen and A. Skou, editors, Proc. International Workshop on Computer Aided Verification, volume 575 of Lecture Notes in Computer Science, pages 410-420. Springer-Verlag, 1991.
Kiyoharu Hamaguchi, Hiromi Hiraishi, and Shuzo Yajima. Design verification of asynchronous sequential circuits using symbolic model checking. In International Symposium on Logic Synthesis and Microprocessor Architecture, pages 84-90, July 1992.
Michael R. Hansen, Zhou Chaochen, and Jørgen Staunstrup. A real-time duration semantics for circuits. In Tau-92: 1992 Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
Takahiro Hanyu, Takahiro Saito, and Michitaka Kameyama. Asynchronous multiple-valued VLSI system based on dual-rail current-mode differential logic. In Proc. IEEE International Symposium on Multiple-Valued Logic, pages 134-139, May 1998.
W. Hardt, B. Kleinjohann, A. Rettberg, and E. Kleinjohann. A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing. In Twelfth Annual IEEE International ASIC/SOC Conference, pages 336-339, 1999.
W. Hardt, M. Visarius, and B. Kleinjohann. Architecture level optimization for asynchronous IPs. In IEEE International ASIC/SOC Conference, September 2000.
O. Hauck and S. A. Huss. Asynchronous wave pipelines for high throughput datapaths. In IEEE International Conference on Electronics, Circuits and Systems, pages 283-286, September 1998.
Scott Hauck, Steven Burns, Geatano Borriello, and Carl Ebeling. An FPGA for implementing asynchronous circuits. IEEE Design & Test of Computers, 11(3):60-69, 1994. (PostScript)
O. Hauck, M. Garg, and S. A. Huss. Asynchronous VLSI architectures for Hufman codecs. In Proc. International Symposium on Circuits and Systems, June 1998.
O. Hauck, M. Garg, and S. A. Huss. Efficient and safe asynchronous wave-pipelines architectures for datapath and control unit applications. In Proc. of the Great Lakes Symposium on VLSI, pages 38-41, March 1999.
O. Hauck, M. Garg, and S. A. Huss. Two-phase asynchronous wave-pipelines and their application to a 2D-DCT. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 219-228, April 1999.
O. Hauck, A. Katoch, and S. A. Huss. VLSI system design using asynchronous wave pipelines: A 0.35 mu m CMOS 1.5 GHz elliptic curve public key cryptosystem chip. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 188-197. IEEE Computer Society Press, April 2000.
Scott Hauck. Asynchronous design methodologies: An overview. Technical Report TR 93-05-07, Department of Computer Science and Engineering, University of Washington, Seattle, 1993. (PostScript)
Scott Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1):69-93, January 1995.
N. M. Hayes, M. S. Tsay, F. D. LaRocca, P. W. Kempsey, S. H. Padnos, T. L Chang, and P. P. Thomas. Asynchronous design integrates address translation and physical data cache for the WE-32201 IMDC. In Proc. International Conf. Computer Design (ICCD), pages 235-237, 1987.
Alan B. Hayes. Stored state asynchronous sequential circuits. IEEE Transactions on Computers, C-30(8):596-600, August 1981.
Alan B. Hayes. Self-timed IC design with PPL's. In Randal Bryant, editor, Proceedings of Third Caltech Conference on VLSI, pages 257-274. Computer Science Press, 1983.
Pieter J. Hazewindus. Testing Delay-Insensitive Circuits. PhD thesis, California Institute of Technology, 1992.
Jifeng He, Geoffrey Brown, Wayne Luk, and John W. O'Leary. Deriving handshake modules for a multi-target hardware compiler. In Designing Correct Circuits, 1996.
Bryan J. Heard, Ramu N. Sheshadri, Ronald B. David, and Arvid G. Sammuli. Automatic test pattern generation for asynchronous networks. In Proc. International Test Conference, pages 63-69. IEEE Computer Society Press, 1984.
Christoph Heer. Synchronous clocked and self-timed pipeline configurations. IEEE Technical Committee on Computer Architecture Newsletter, October 1995.
Matthias Heinitz. Fault Simulation for Asynchronous Circuits. PhD thesis, Dept. of Elec. and Info., University of Hannover, August 2000.
A. Hemani, T. Meincke, S. Kumar, A. Postula, T. Olsson, P. Nilsson, J. Öberg, P. Ellervee, and D. Lundqvist. Lowering power consumption in clock by using globally asynchronous, locally synchronous design style. In Proc. ACM/IEEE Design Automation Conference, 1999.
Matthew Hennessy. Synchronous and asynchronous experiments on processes. Inform. and Control, 59:36-83, 1983.
M. Hennessy. An algebraic theory of fair asynchronous communicating processes. Theoretical Computer Science, 49:121-143, 1987.
M. Hevery. Asynchronous circuit completion detection by current sensing. In Twelfth Annual IEEE International ASIC/SOC Conference, pages 322-326, 1999.
Masaharu Hirayama. A silicon compiler system based on asynchronous architecture. IEEE Transactions on Computer-Aided Design, 6(3):297-304, May 1987.
Ron Ho, John Gainsley, and Robert Drost. Long wires and asynchronous control. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 240-249. IEEE Computer Society Press, April 2004.
C. A. R. Hoare. Communicating sequential processes. Communications of the ACM, 21(8):666-677, August 1978.
C. A. R. Hoare. Communicating Sequential Processes. Prentice-Hall, 1985.
J. M. Hoke, P. W. Bond, T. Lo, F. S. Pidala, and G. Steinbrueck. Self-timed interface for S/390 I/O subsystem interconnection. IBM Journal of Research and Development, 43(5/6):829-846, 1999. (PDF)
J. M. Hoke, P. W. Bond, R. R. Livolsi, T. C. Lo, F. S. Pidala, and G. Steinbrueck. Self-timed interface of the input/output subsystem of the IBM eserver z900. IBM Journal of Research and Development, 46(4/5):447-460, 2002. (PDF)
Lee A. Hollaar. Direct implementation of asynchronous control units. IEEE Transactions on Computers, C-31(12):1133-1141, December 1982.
D. Hormdee and J. D. Garside. AMULET3i cache architecture. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 152-161. IEEE Computer Society Press, March 2001.
D. Hormdee, J. D. Garside, and S. B. Furber. An asynchronous copy-back cache architecture. Microprocessors and Microsystems, 27(10):485-500, November 2003.
D. Hormdee. An analysis of asynchronous microprocessor pipelines. Master's thesis, Department of Computer Science, University of Manchester, 1998.
D. Hormdee. Copy-Back Cache Organisation For An Asynchronous Microprocessor. PhD thesis, Department of Computer Science, University of Manchester, 2002. (PDF)
Jens U. Horstmann, Hans W. Eichel, and Robert L. Coates. Metastability behavior of CMOS ASIC flip-flops in theory and test. IEEE Journal of Solid-State Circuits, 24(1):146-157, February 1989.
G. N. Hoyer and C. Sechen. A locally-clocked dynamic logic serial/parallel multiplier. In Proc. IEEE Custom Integrated Circuits Conference, pages 481-484, 2000.
G. Hoyer, G. Yee, and C. Sechen. Locally-clocked dynamic logic. In Proc. of the Midwest Symposium on Circuits and Systems, pages 18-21, August 1998.
Gregg N. Hoyer, Gin Yee, and Carl Sechen. Locally clocked pipelines and dynamic logic. IEEE Transactions on VLSI Systems, 10(1):58-62, February 2001.
Calvin J. A. Hsia and C. Y. Roger Chen. Synthesis of asynchronous circuits --- testing unique circuit behavior of signal transition graphs. In Proc. International Symposium on Circuits and Systems, pages 1074-1077, 1995.
C. G. Huang, C. G. Jesshope, and I. M. Nedelchev. Systematic method for synthesising purely delay-insensitive circuits. IEE Proceedings, Computers and Digital Techniques, 140(5):269-276, September 1993.
Hong-Yi Huang, Kuo-Hsing Cheng, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, and Chung-Yu Wu. Low-voltage low-power CMOS true-single-phase clocking scheme with locally asynchronous logic circuits. In Proc. International Symposium on Circuits and Systems, pages 1572-1575, 1995.
J. L. Huertas and J. I. Acha. Self-synchronization of asynchronous sequential circuits employing a general clock function. IEEE Transactions on Computers, C-25(3):297-300, 1976.
J. L. Huertas and J. I. Acha. Synthesis of p-valued asynchronous sequential circuits by using a general clock function. In Proceedings of the 6th International Symposium on Multi-Valued Logic, pages 102-109, May 1976.
D. A. Huffman. The synthesis of sequential switching circuits. In E. F. Moore, editor, Sequential Machines: Selected Papers. Addison-Wesley, 1964.
Henrik Hulgaard and Tod Amon. Symbolic timing analysis of asynchronous systems. IEEE Transactions on Computer-Aided Design, 19(10):1093-1104, October 2000.
Henrik Hulgaard and Steven M. Burns. Bounded delay timing analysis of a class of CSP programs with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2-11, November 1994. (PostScript)
Henrik Hulgaard and Steven M. Burns. Efficient timing analysis of a class of Petri nets. In Proc. International Workshop on Computer Aided Verification. Springer-Verlag, 1995. (PostScript)
Henrik Hulgaard and Steven M. Burns. Bounded delay timing analysis of a class of CSP programs. Formal Methods in System Design, 11(3):265-294, October 1997.
Henrik Hulgaard, Steven M. Burns, Tod Amon, and Gaetano Borriello. Practical applications of an efficient time separation of events algorithm. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 146-151, 1993. (PostScript)
Henrik Hulgaard, Tod Amon, Steven M. Burns, and Gaetano Borriello. Timing analysis of timed event graphs with bounded delays using algebraic techniques. In Proceedings of IEEE Conference on Decision and Control, 1994. (PostScript)
Henrik Hulgaard, Steven M. Burns, and Gaetano Borriello. Testing asynchronous circuits: A survey. Technical Report TR 94-03-06, Department of Computer Science and Engineering, University of Washington, Seattle, 1994. (PostScript)
H. Hulgaard, S. M. Burns, T. Amon, and G. Borriello. An algorithm for exact bounds on the time separation of events in concurrent systems. IEEE Transactions on Computers, 44(11):1306-1317, November 1995.
Henrik Hulgaard, Steven M. Burns, and Gaetano Borriello. Testing asynchronous circuits: A survey. Integration, the VLSI journal, 19(3):111-131, November 1995.
Henrik Hulgaard. Timing Analysis and Verification of Timed Asynchronous Circuits. PhD thesis, Department of Computer Science, University of Washington, 1995.
Andy Hung and Teresa H.-Y. Meng. Asynchronous self-timed circuit synthesis with timing constraints. In Proc. International Symposium on Circuits and Systems, volume 2, pages 1126-1130, May 1990.
B. W. Hunt, K. S. Stevens, B. W. Suter, and D. S. Gelosh. A single chip low power asynchronous implementation of an FFT algorithm for space applications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 216-223, 1998.
J. F. Hurdle. Self-timed neural model implementation: An example using CMAC. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
M. Hurtado and D. L. Elliott. Ambiguous behavior of logic bistable systems. In Proceedings of the 13th Annual Allerton Conference on Circuit & System Theory, pages 605-611, October 1975.
Marco Hurtado. Structure and Performance of Asymptotically Bistable Dynamical Systems. PhD thesis, Sever Institute of Technology, Washington Univ., St. Louis, MO, 1975.
Wei Hwang, Walter H. Henkels, and Rajiv V. Joshi. A pulse-to-static conversion latch with a self-timed control circuit. In Proc. International Conf. Computer Design (ICCD), pages 712-717, October 1997.
Wei Hwang, Rajiv V. Joshi, and George D. Gristede. A scannable pulse-to-static conversion register array for self-timed circuits. IEEE Journal of Solid-State Circuits, 35(1):125-128, January 2000.
M. Imai, M. Ozcan, and T. Nanya. Evaluation of delay variance in asynchronous circuits based on the scalable-delay-insensitive model. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 62-71. IEEE Computer Society Press, April 2004.
N. Ishiura, M. Takahashi, and S. Yajim. Time-symbolic simulation for accurate timing verification of asynchronous behavior of logic circuits. In Proc. ACM/IEEE Design Automation Conference, pages 497-502, 1989.
Pasi Isotalus. 16x16 bit multiplier comparison report. Technical report, Tampere University of Technology, Finland, 1997.
O. A. Izosimov, I. I. Shagurin, and V. V. Tsylyov. Physical approach to CMOS module self-timing. Electronics Letters, 26(22):1835-1836, October 1990.
A. H. Jackson and A. M. Tyrrell. Asynchronous embryonics. In D. Keymeulen et al., editors, Proceedings of the 3rd NASA/DoD Conference on Evolvable Hardware, pages 201-210. IEEE Computer Society Press, 2001.
A. H. Jackson and A. M. Tyrrell. Asynchronous embryonics with reconfiguration. In Y. Liu et al., editors, Evolvable Systems: From Biology to Hardware (ICES), volume 2210 of Lecture Notes in Computer Science, pages 88-99. Springer-Verlag, 2001.
A. H. Jackson and A. M. Tyrrell. Implementing asynchronous embryonic circuits using AARDVArc. In Proceedings of the NASA/DoD Conference on Evolvable Hardware, pages 231-240, July 2002.
D. L. Jackson, R. Kelly, and L. E. M. Brackenbury. Differential register bank design for self-timed differential bipolar technology. IEE Proceedings, Circuits, Devices and Systems, 144(5), October 1997.
G. M. Jacobs and R. W. Brodersen. Self-timed integrated circuits for digital signal processing applications. In Robert W. Brodersen and Howard S. Moscovitz, editors, VLSI Signal Processing, III. IEEE Press, 1988.
Gordon M. Jacobs and Robert W. Brodersen. A fully asynchronous digital signal processor using self-timed circuits. IEEE Journal of Solid-State Circuits, 25(6):1526-1537, December 1990.
Gordon M. Jacobs. Self-Timed Integrated Circuits for Digital Signal-Processing. PhD thesis, University of California, Berkeley, November 1989.
Hans Jacobson and Ganesh Gopalakrishnan. Asynchronous microengines for efficient high-level control. In Advanced Research in VLSI, pages 201-218, September 1997.
Hans Jacobson and Ganesh Gopalakrishnan. Asynchronous microengines for efficient high-level control. Technical Report UUCS-97-007, Dept. of Computer Science, University of Utah, June 1997.
Hans M. Jacobson and Ganesh Gopalakrishnan. Application-specific programmable control for hihg-performance asynchronous circuits. Proceedings of the IEEE, 87(2):319-331, February 1999. Corrections in Proc IEEE March 1999, p. 525.
Hans Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, and Prabhakar Kudva. High-level asynchronous system design using the ACK framework. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 93-103. IEEE Computer Society Press, April 2000.
Hans Jacobson, Chris J. Myers, and Ganesh Gopalakrishnan. Achieving fast and exact hazard-free logic minimization of extended burst-mode gc finite state machines. In Proc. International Conf. Computer-Aided Design (ICCAD), November 2000.
Hans M. Jacobson, Prabhakar N. Kudva, Pradip Bose, Peter W. Cook, Stanley E. Schuster, Eric G. Mercer, and Chris J. Myers. Synchronous interlocked pipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 3-12, April 2002.
K. W. James and K. Y. Yun. Average-case optimized transistor-level technology mapping of extended burst-mode circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 70-79, 1998. (PostScript) (PDF)
Kenneth J. Janik. A Microarchitecture Study of the Counterflow Pipeline Principle. PhD thesis, Oregon State University, February 1998.
B. Javadi, M. Naderi, H. Pedram, A. Afzali-Kusha, and M.K. Akbari. An asynchronous Viterbi decoder for low-power applications. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 141-150, September 2003.
C. R. Jesshope, I. M. Nedelchev, and C. G. Huang. Compilation of process algebra expressions into delay-insensitive circuits. IEE Proceedings, Computers and Digital Techniques, 140(5):261-268, September 1993.
R. Jiménez, A.J. Acosta, A. Barriga, M.J. Bellido, and M. Valencia. Efficient self-timed circuits based on weak NMOS-trees. In IEEE International Conference on Electronics, Circuits and Systems, pages 179-182, 1998.
F. Jiménez, N. Harchani, M. Courvoisier, M. Al-Mohamed, A. Garcia, D. Esteve, and G Munoz. Tools and models for systems design and synthesis of mems based on asynchronous circuits. In Proceedings of IEEE International Conference on Industrial Technology, pages 64-69, 2000.
R. Jiménez, A. J. Acosta, E. J. Peralías, and A. Rueda. An application of self-timed circuits to the reduction of switching noise in analog-digital circuits. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 1918 of Lecture Notes in Computer Science, pages 295-305, September 2000.
D. Johnson and V. Akella. Design and analysis of asynchronous adders. IEE Proceedings, Computers and Digital Techniques, 145(1):1-8, 1998.
David Johnson, Venkatesh Akella, and Brett Stott. Micropipelined asynchronous discrete cosine transform (DCT/IDTC) processor. IEEE Transactions on VLSI Systems, 6(4):731-740, December 1998.
Tin-Chak Johnson-Pang, Chiu-Sing Choy, Cheong-Fat Chan, and Wai-Kuen Cham. Self-timed Booth's multiplier. In Proceedings of 2nd International Conference on ASIC, pages 280-283, Shanghai, China, October 1996.
J. M. Johnson. Theory and Application of Self-Timed Integrated Systems using Ternary Logic Elements. PhD thesis, Electrical and Computer Engineering, University of California, Santa Barbara, December 1988.
Gjalt de Jong and Bill Lin. A communicating Petri net model for the design of concurrent asynchronous modules. In Proc. ACM/IEEE Design Automation Conference, pages 49-55, June 1994.
Bengt Jonsson. A model and proof system for asynchronous networks. In Proceedings of the 4th ACM Symposium on Principles of Distributed Computing, pages 49-58, 1985.
Bengt Jonsson. A fully abstract trace model for dataflow networks. Research Report SICS R88016, Swedish Institute of Computer Science, November 1988.
Mark B. Josephs and Andrew M. Bailey. The use of SI-algebra in the design of sequencer circuits. Formal Aspects of Computing, 9(4):395-408, 1997.
M. B. Josephs and D. P. Furey. Delay-insensitive interface specification and synthesis. In Proc. Design, Automation and Test in Europe (DATE), pages 169-173, March 2000.
Mark B. Josephs and Dennis P. Furey. A programming approach to the design of asynchronous logic blocks. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 34-60. Springer-Verlag, 2002.
Mark B. Josephs and Jan Tijmen Udding. An algebra for delay-insensitive circuits. In Robert P. Kurshan and Edmund M. Clarke, editors, Proc. International Workshop on Computer Aided Verification, volume 531 of Lecture Notes in Computer Science, pages 343-352. Springer-Verlag, 1990.
Mark B. Josephs and Jan Tijmen Udding. Delay-insensitive circuits: An algebraic approach to their design. In J. C. M. Baeten and J. W. Klop, editors, CONCUR '90, Theories of Concurrency: Unification and Extension, volume 458 of Lecture Notes in Computer Science, pages 342-366. Springer-Verlag, August 1990.
Mark B. Josephs and Jan Tijmen Udding. The design of a delay-insensitive stack. In G. Jones and M. Sheeran, editors, Designing Correct Circuits, pages 132-152. Springer-Verlag, 1990.
Mark B. Josephs and Jan Tijmen Udding. An algebra for delay-insensitive circuits. In E. M. Clarke and R. P. Kurshan, editors, Proc. International Workshop on Computer Aided Verification, pages 147-176. American Mathematical Society, 1991. (DVI)
M. B. Josephs and J. T. Udding. An overview of DI algebra. In T. N. Mudge, V. Milutinovic, and L. Hunter, editors, Proc. Hawaii International Conf. System Sciences, volume I, pages 329-338. IEEE Computer Society Press, January 1993. (DVI)
Mark B. Josephs and Jan Tijmen Udding. Implementing a stack as a delay-insensitive circuit. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 123-135. Elsevier Science Publishers, 1993.
M. B. Josephs and A. V. Yakovlev. Handouts of the ACiD-WG workshop. Technical Report CS-670, University of Newcastle upon Tyne, April 1999.
Mark B. Josephs and Jelio T. Yantchev. CMOS design of the tree arbiter element. IEEE Transactions on VLSI Systems, 4(4):472-476, December 1996.
Mark B. Josephs, C. A. R. Hoare, and He Jifeng. A theory of asynchronous processes. Technical Report PRG-TR-6-89, Oxford Univ., Computing Laboratory, 1989.
Mark B. Josephs, Rudolf H. Mak, and Tom Verhoeff. Asynchronous design of a router. In J. P. Veen, editor, Proc. of the IEEE/ProRISC Symposium on Circuits, Systems and Signal Processing, pages 173-179, Utrecht, Netherlands, 1991. Stichting voor de Technische Wetenschappen.
Mark B. Josephs, Rudolf H. Mak, Jan Tijmen Udding, Tom Verhoeff, and Jelio T. Yantchev. High-level design of an asynchronous packet-routing chip. In Jørgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 261-274. Elsevier Science Publishers, 1992.
Mark B. Josephs, Jan Tijmen Udding, and Yelio Yantchev. Handshake algebra. Technical Report SBU-CISM-93-1, School of Computing, Information Systems and Mathematics, South Bank University, London, December 1993.
M. B. Josephs, P. G. Lucassen, J. T. Udding, and T. Verhoeff. Formal design of an asynchronous DSP counterflow pipeline: A case study in handshake algebra. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 206-215, November 1994. (PDF) (DVI)
Mark B. Josephs, Steven M. Nowick, and C. H. (Kees) van Berkel. Modeling and design of asynchronous circuits. Proceedings of the IEEE, 87(2):234-242, February 1999.
Mark B. Josephs. Receptive process theory. Acta Informatica, 29(1):17-31, 1992.
Mark B. Josephs. Formal derivation of a loadable asynchronous counter. In Mathematics of Program Construction, Lecture Notes in Computer Science. Springer-Verlag, 1998.
Mark B. Josephs. An analysis of determinacy using a trace-theoretic model of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 121-130. IEEE Computer Society Press, May 2003.
Shyh-Jye Jou and I.-Yao Chung. Low-power global asynchronous locally synchronous design using self-timed circuit technology. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1808-1811, June 1997.
Shyh Jye Jou and I. Yao Chung. Low-power self-timed circuit design technique. Electronics Letters, 33(2):110-111, 1997.
Jer Min Jou, Ren Der Chen, and Ke Ming Lin. An integrated synthesis system for speed-independent asynchronous circuits. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1600-1603, June 1997.
J. Robert Jump and P. S. Thiagarajan. On the equivalence of asynchronous control structures. In Annual Symposium on Switching and Automata Theory, pages 212-223. IEEE Computer Society Press, 1972.
J. Robert Jump and P. S. Thiagarajan. On the equivalence of asynchronous control structures. SIAM Journal on Computing, 2:67-87, 1973.
J. Robert Jump and P. S. Thiagarajan. On the interconnection of asynchronous control structures. Journal of the ACM, 22:596-612, October 1975.
Sung Tae Jung and Chu Shik Jhon. Direct synthesis of efficient speed-independent circuits from deterministic signal transition graphs. In Proc. International Symposium on Circuits and Systems, pages 307-310, June 1994.
Sung Tae Jung and Chris J. Myers. Direct synthesis of timed asynchronous circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 332-337, November 1999.
Sung Tae Jung and Chris J. Myers. Direct synthesis of timed circuits from free-choice STGs. IEEE Transactions on Computer-Aided Design, 21(3):275-290, March 2002.
Sung Tae Jung, Uun Sei Park, Junk Sik Kim, and Chu Shik Jhon. Automatic synthesis of gate-level speed-independent control circuits from signal transition graphs. In Proc. International Symposium on Circuits and Systems, pages 1411-1414, 1995.
Sung Tae Jung. Direct synthesis of timed asynchronous circuits. In Proc. International Workshop on Logic Synthesis, June 1999.
Hiroto Kagotani and Takashi Nanya. A synthesis method of quasi-delay-insensitive processors based on dependency graph. In Asia-Pacific Conference on Hardware Description Languages (APCHDL), pages 177-184, October 1994.
Hiroto Kagotani, Takuji Okamoto, and Takashi Nanya. Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. In Proc. of Asia and South Pacific Design Automation Conference, pages 425-430, February 2001.
A. P. Kakaroudas, K. Papadomanolakis, V. Kokkinos, and C. E. Goutis. Comparative study on self-checking carry-propagate adders in terms of area, power and performance. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 1918 of Lecture Notes in Computer Science, pages 187-194, September 2000.
Anne Kaldewaij. A Formalism for Concurrent Processes. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1986.
Y. Kameda, S. Polonsky, M. Maezawa, and T. Nanya. Primitive-level pipelining method on delay-insensitive model for RSFQ pulse-driven logic. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 262-273, 1998.
Y. Kameda, S. V. Polonsky, M. Maezawa, and T. Nanya. Self-timed parallel adders based on DI RSFQ primitives. IEEE Transactions on Applied Superconductivity, 9(2):4040-4045, June 1999.
Y. Kameda, S.V. Polonsky, M. Maezawa, and T. Nanya. Self-timed parallel adders based on DI RSFQ primitives. IEEE Transactions on Applied Superconductivity, 9(2):4040-4045, June 1999.
J.-W. Kang, C.-L. Wey, and P. D. Fisher. An efficient modelling and synthesis procedure of asynchronous sequential logic circuits. In Proc. of the Midwest Symposium on Circuits and Systems, pages 512-515, 1992.
Jun-Woo Kang, Chin-Long Wey, and P. David Fisher. A synthesis procedure for large-scale asynchronous finite state machines. In Proc. of the Midwest Symposium on Circuits and Systems, pages 1304-1307, 1993.
J.-W. Kang, P. D. Fisher, and C.-L. Wey. Efficient modelling and synthesis procedure of asynchronous sequential logic elements. IEE Proceedings, Computers and Digital Techniques, 141(1):61-64, January 1994.
Jun-Woo Kang, Chin-Long Wey, and P. David Fisher. Application of bipartite graphs for achieving race-free state assignments. IEEE Transactions on Computers, 44(8):1002-1011, August 1995.
J.-W. Kang. The modeling and synthesis of asynchronous sequential logic circuits. PhD thesis, Dept. of Electrical Engineering, Michigan State univ., 1993.
Jin-Ku Kang. Self-timed pipelining using latest arriving signal detection. Electronics Letters, 37(10):615-617, May 2001.
Vitit Kantabutra and Andreas G. Andreou. A state assignment approach to asynchronous CMOS circuit design. IEEE Transactions on Computers, 43(4):460-469, April 1994.
Per Arne Karlsen and Per Torstein Røine. A timing verifier and timing profiler for asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 13-23, April 1999.
Per Arne Karlsen. A system for timing verification of asynchronous circuits. Master's thesis, Department of Informatics, University of Oslo, 1998.
S. Karthik, I. de Souza, J. T. Rahmeh, and J. A. Abraham. Interlock schemes for micropipelines: Application to a self-timed rebound sorter. In Proc. International Conf. Computer Design (ICCD), pages 393-396. IEEE Computer Society Press, 1991.
M. R. Karthikeyan and S. K. Nandy. An asynchronous architecture for digital signal processors. In Proc. European Design and Test Conference, page 615, 1997.
Alireza Kaviani. Phase alignment using asynchronous state machines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 86-94. IEEE Computer Society Press, April 2004.
David Kearney and Neil W. Bergmann. Bundled data asynchronous multipliers with data dependant computation times. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 186-197. IEEE Computer Society Press, April 1997.
David Kearney and Neil W. Bermann. Performance evaluation of asynchronous logic pipelines with data dependant processing delays. In Asynchronous Design Methodologies, pages 4-13. IEEE Computer Society Press, May 1995.
D. Kearney. Theoretical limits on the data dependent performance of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 201-207, April 1999.
Robert M. Keller. On the decomposition of asynchronous modules. In Annual Symposium on Switching and Automata Theory, pages 78-89. IEEE Computer Society Press, 1972.
Robert M. Keller. Towards a theory of universal speed-independent modules. IEEE Transactions on Computers, C-23(1):21-33, January 1974.
Eric Keller. Building asynchronous circuits with jbits. In Field-Programmable Logic and Applications (FPL2001), volume 2147 of Lecture Notes in Computer Science, pages 628-632, 2001.
R. Kelly and L. E. M. Brackenbury. Design and modelling of a high performance differential bipolar self-timed microprocessor. IEE Proceedings, Computers and Digital Techniques, 144(6):371-380, November 1997.
Clinton Kelly, Virantha Ekanayake, and Rajit Manohar. SNAP: A sensor-network asynchronous processor. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 24-33. IEEE Computer Society Press, May 2003.
Robert Kelly. Asynchronous design aspects of high-performance logic: Architectural modelling of a bipolar asynchronous microprocessor. Master's thesis, Department of Computer Science, University of Manchester, 1995.
Christoph Kern, Tarik Ono-Tesfaye, and Mark Greenstreet. A light-weight framework for hardware verification. In The Fifth Annual Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS'99, volume 1579 of Lecture Notes in Computer Science, pages 330-344, Amsterdam, The Netherlands, March 1999. Springer.
Joep Kessels and Paul Marston. Designing asynchronous standby circuits for a low-power pager. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 268-278. IEEE Computer Society Press, April 1997.
Joep Kessels and Paul Marston. Designing asynchronous standby circuits for a low-power pager. Proceedings of the IEEE, 87(2):257-267, February 1999.
Joep Kessels and Ad Peeters. The Tangram framework: Asynchronous circuits for low power. In Proc. of Asia and South Pacific Design Automation Conference, pages 255-260, February 2001.
Joep Kessels, Kees van Berkel, Ronan Burgess, Marly Roncken, and Frits Schalij. An error decoder for the compact disc player as an example of VLSI programming. In Proc. European Conference on Design Automation (EDAC), pages 69-74, March 1992.
Joep Kessels, Torsten Kramer, Gerrit den Besten, Ad Peeters, and Volker Timm. Applying asynchronous circuits in contactless smart cards. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 36-44. IEEE Computer Society Press, April 2000.
Joep Kessels, Torsten Kramer, Ad Peeters, and Volker Timm. DESCALE: a design experiment for a smart card application consuming low energy. In Rene van Leuken, Reinder Nouta, and Alexander de Graaf, editors, European Low Power Initiative for Electronic System Design, pages 247-262. Delft Institute of Microelectronics and Submicron Technology, July 2000.
Joep Kessels, Torsten Kramer, Ad Peeters, and Volker Timm. DESCALE: a design experiment for a smart card application consuming low energy. In Jens Sparsø and Steve Furber, editors, Principles of Asynchronous Circuit Design: A Systems Perspective, chapter 13. Kluwer Academic Publishers, 2001.
Joep Kessels, Ad Peeters, Torsten Kramer, Markus Feuser, and Klaus Ully. Designing an asynchronous bus interface. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 108-117. IEEE Computer Society Press, March 2001.
Joep Kessels, Ad Peeters, Paul Wielage, and Suk-Jin Kim. Clock synchronization through handshake signalling. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 59-68, April 2002. (PDF)
Joep Kessels, Ad Peeters, and Suk-Jin Kim. Bridging clock domains by synchronizing the mice in the mousetrap. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 141-150, September 2003.
Joep Kessels, Ad Peeters, Paul Wielage, and Suk-Jin Kim. Clock synchronization through handshake signalling. Microprocessors and Microsystems, 27(9):447-460, October 2003.
Joep Kessels. VLSI programming of a low-power asynchronous Reed-Solomon decoder for the DCC player. In Asynchronous Design Methodologies, pages 44-52. IEEE Computer Society Press, May 1995.
Joep L. W. Kessels. Calculational derivation of a counter with bounded response time and bounded power dissipation. Distributed Computing, 8(3):143-149, 1995.
Kurt Keutzer, Luciano Lavagno, and Alberto Sangiovanni-Vincentelli. Synthesis for testability techniques for asynchronous circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 326-329. IEEE Computer Society Press, November 1991.
Kurt Keutzer, Luciano Lavagno, and Alberto Sangiovanni-Vincentelli. Synthesis for testability techniques for asynchronous circuits. IEEE Transactions on Computer-Aided Design, 14(12):1569-1577, December 1995.
Ajay Khoche and Erik Brunvand. Testing self-timed circuits using scan paths. In 5th NASA Symposium on VLSI Design, November 1993.
Ajay Khoche and Erik Brunvand. Testing micropipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 239-246, November 1994.
Ajay Khoche and Erik Brunvand. A partial scan methodology for testing self-timed circuits. In Proc. IEEE VLSI Test Symposium, pages 283-289, 1995.
Ajay Khoche and Erik Brunvand. Testing self-timed circuits using partial scan. In Asynchronous Design Methodologies, pages 160-169. IEEE Computer Society Press, May 1995.
Ajay Khoche and Erik Brunvand. Critical hazard free test generation for asynchronous circuits. In Proc. IEEE VLSI Test Symposium, pages 203-208, 1997.
Ajay Khoche. Testing Macro-module based Self-timed Circuits. PhD thesis, The University of Utah, 1996.
A. Yu. Kidiyarova-Shevchenko, K. Yu. Platov, E.M. Tolkacheva, and I.A. Kateava. RSFQ asynchronous serial multiplier and spreading codes generator for multiuser detector. IEEE Transactions on Applied Superconductivity, 13(2):429-432, June 2003.
Sangyun Kim and Peter A. Beerel. Pipeline optimization for asynchronous circuits: Complexity analysis and an efficient optimal algorithm. In Proc. International Conf. Computer-Aided Design (ICCAD), November 2000.
Do-Wan Kim and Deog-Kyoon Jeong. Iterative self-timed multiplier with early completion. In Proc. European Solid-State Circuits Conference (ESSCIRC), September 2000. (PDF)
Woo Jin Kim and Yong-Bin Kim. Automating wave-pipelined circuit design. IEEE Design & Test of Computers, 20(6):51-58, 2003.
Uisok Kim and Dong-Ik Lee. Practical synthesis of speed-independent circuits using unfoldings. In Proc. of Asia and South Pacific Design Automation Conference, pages 191-196, February 1998.
Seokjin Kim and Ramalingam Sridhar. Hierarchical synchronization scheme using self-timed mesochonous interconnections. In Proc. International Symposium on Circuits and Systems, pages 1824-1827, June 1997.
Euiseok Kim, Jeong-Gun Lee, and Dong-Ik Lee. Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis. In Proc. International Symposium on Circuits and Systems, pages 49-52, 2000.
Euiseok Kim, Jeong-Gun Lee, and Dong-Ik Lee. Automatic process-oriented control circuit generation for asynchronous high-level synthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 104-113. IEEE Computer Society Press, April 2000.
Kyeounsoo Kim, Peter A. Beerel, and Youpyo Hong. An asynchronous matrix-vector multiplier for discrete cosine transform. In International Symposium on Low Power Electronics and Design, pages 256-261, July 2000.
Euiseok Kim, Jeong-Gun Lee, and Dong-Ik Lee. Building a distributed asynchronous control unit through automatic derivation of hierarchically decomposed ASFMs from a CDFG. In Advanced Research in VLSI, pages 2-15, March 2001.
Hoshik Kim, Peter A. Beerel, and Ken Stevens. Relative timing based verification of timed circuits and systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 115-124, April 2002.
Hoshik Kim. Relative timing based verification of timed circuits and systems. In Proc. International Workshop on Logic Synthesis, June 1999.
Izumi Kimura. Extensions of asynchronous circuits and the delay problem I: Good extensions and the delay problem of the first kind. Journal of Computer and System Sciences, 2(3):251-287, October 1968.
Izumi Kimura. Extensions of asynchronous circuits and the delay problem II: Spike-free extensions and the delay problem of the second kind. Journal of Computer and System Sciences, 5(2):129-162, April 1971.
D. J. Kinniment and J. V. Woods. Synchronization and arbitration circuits in digital systems. Proceedings of the IEE, 123(10):961-966, October 1976.
D. J. Kinniment, J. D. Garside, and B. Gao. A comparison of power consumption in some CMOS adder circuits. In Power and Timing Modeling, Optimization and Simulation (PATMOS), October 1995. (PostScript)
D. J. Kinniment, B. Gao, A. V. Yakovlev, and F. Xia. Toward asynchronous A-D conversion. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 206-215, 1998.
David Kinniment, Alex Yakovlev, and Bo Gao. Synchronous and asynchronous A-D conversion. IEEE Transactions on VLSI Systems, 8(2):217-220, April 2000.
D. J. Kinniment, O. V. Maevsky, A. Bystrov, G. Russell, and A. V. Yakovlev. On-chip structures for timing measurements and test. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 190-197, April 2002.
David J. Kinniment, Alexandre Bystrov, and Alexandre Yakovlev. Synchronization circuit performance. IEEE Journal of Solid-State Circuits, 37(2):202-209, February 2002.
D. J. Kinniment, O. V. Maevsky, A. Bystrov, G. Russell, and A. V. Yakovlev. On-chip structures for timing measurement and test. Microprocessors and Microsystems, 27(9):473-483, October 2003.
D. J. Kinniment. An evaluation of asynchronous addition. IEEE Transactions on VLSI Systems, 4(1):137-140, March 1996.
A. F. Kirichenko. High-speed asynchronous data multiplexing/demultiplexing. IEEE Transactions on Applied Superconductivity, 9(2):4046-4-48, June 1999.
Michael Kishinevsky and Jørgen Staunstrup. Characterizing speed-independence of high-level designs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 44-53, November 1994. (PostScript)
Michael Kishinevsky and Jørgen Staunstrup. Mechanized verification of speed-independence. In Proc. of the 2nd Workshop on Theorem Provers in Circuit Design, pages 229-248, Bad Herrenalb, Germany, September 1994. (PostScript)
M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. Analysis and identification of self-timed circuits. In Jørgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 275-287. Elsevier Science Publishers, 1992.
M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. On self-timed behavior verification. In Proceedings of ACM TAU 92, March 1992.
M. Kishinevsky, A. Kondratyev, A. Taubin, and V. Varshavsky. Analysis and identification of speed-independent circuits on an event model. Formal Methods in System Design, 4(1):33-75, 1994. (PostScript)
M. A. Kishinevsky, A. Y. Kondratyev, and A. R. Taubin. Specification and analysis of self-timed circuits. Journal of VLSI Signal Processing, 7(1/2):117-135, February 1994.
Michael Kishinevsky, Alex Kondratyev, Alexander Taubin, and Victor Varshavsky. Concurrent Hardware: The Theory and Practice of Self-Timed Design. Series in Parallel Computing. John Wiley & Sons, 1994.
Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, and Alex Yakovlev. Coupling asynchrony and interrupts: Place chart nets and their synthesis. In Pierre Azéma and Gianfranco Balbo, editors, International Conference on Applications and Theory of Petri Nets, volume 1248 of Lecture Notes in Computer Science, pages 328-347, Toulouse, France, June 1997. Springer-Verlag.
Michael Kishinevsky, Luciano Lavagno, Alexander Saldanha, and Alexander Taubin. Partial scan delay-fault testing of asynchronous circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), November 1997.
M. Kishinevsky, J. Cortadella, and A. Kondratyev. Asynchronous interface specification, analysis and synthesis. In Proc. ACM/IEEE Design Automation Conference, pages 2-7, June 1998.
Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alex Saldanha, and Alexander Taubin. Partial-scan delay fault testing of asynchronous circuits. IEEE Transactions on Computer-Aided Design, 17(11):1184-1199, November 1998.
B. R. Kishore and T. Nanya. On concurrent error detection of asynchronous circuits using mixed-signal approach. IEICE Transactions on Information and Systems, E80-D(3):351-362, March 1997.
B. R. Kishore, Y. Kameda, and T. Nanya. A mixed-signal approach for on-line testing of asynchronous circuits--a case study. In Proceedings of 3rd IEEE International On-line Testing Workshop, pages 91-95, July 1997.
Lindsay Kleeman and Antonio Cantoni. Can redundancy and masking improve the performance of synchronizers. IEEE Transactions on Computers, 35:643-646, July 1986.
Lindsay Kleeman and Antonio Cantoni. Metastable behavior in digital systems. IEEE Design & Test of Computers, 4:4-19, December 1987.
Lindsay Kleeman and Antonio Cantoni. On the unavoidability of metastable behavior in digital systems. IEEE Transactions on Computers, C-36(1):109-112, January 1987.
Lindsay Kleeman. Service and Metastability Performance of Arbiters. PhD thesis, Dept. of Electrical and Computer Eng., Univ. of Newcastle, Australia, August 1986.
Uming Ko, P. T. Balsara, and Wai Lee. A self-timed method to minimize spurious transitions in low power CMOS circuits. In John H. Wuorinen, editor, 1994 IEEE Symposium on Low-Power Electronics, pages 62-63, October 1994.
Toshifumi Kobayashi, Kazutami Arimoto, Yuto Ikeda, Masahiro Hatanaka, Koichiro Mashiko, Michihiro Yamada, and Takao Nakano. A high-speed 46Kx4 CMOS DRAM using on-chip self-timing techniques. IEEE Journal of Solid-State Circuits, 21(5):655-661, October 1986.
Zvi Kohavi. Switching and Finite Automata Theory. McGraw-Hill, 1978.
Rakefet Kol and Ran Ginosar. A doubly-latched asynchronous pipeline. In Proc. International Conf. Computer Design (ICCD), pages 706-711, October 1996.
Rakefet Kol and Ran Ginosar. Avid execution in the asynchronous processor Kin. In 3rd Euromicro Conference on Massively Parallel Computing Systems, April 1998.
Rakefet Kol and Ran Ginosar. Kin: A high performance asynchronous processor architecture. In 12th ACM International Conference on Supercomputing, pages 433-440, July 1998.
R. Kol, R. Ginosar, and G. Samuel. Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. (PostScript)
R. Kol, R. Ginosar, and G. Samuel. Statechart methodology for the design, validation and synthesis of large scale asynchronous systems. IEICE Transactions on Information and Systems, E80-D(3):308-314, March 1997.
Tilman Kolks, Steven Vercauteren, and Bill Lin. Control resynthesis for control-dominated asynchronous designs. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, March 1996.
Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Katsuhiko Asada, and Hiroaki Terada. An elastic pipeline mechanism by self-timed circuits. IEEE Journal of Solid-State Circuits, 23(1):111-117, February 1988.
Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, Tetsuo Yamasaki, Kenji Shima, Hiroaki Nishikawa, and Hiroaki Terada. A 40-MFLOPS 32-bit floating-point processor with elastic pipeline scheme. IEEE Journal of Solid-State Circuits, 24(5):1341-1347, October 1989.
Alex Kondratyev and Kelvin Lwin. Design of asynchronous circuits by synchronous CAD tools. In Proc. ACM/IEEE Design Automation Conference, June 2002.
Alex Kondratyev and Kelvin Lwin. Design of asynchronous circuits using synchronous CAD tools. IEEE Design & Test of Computers, 19(4):107-117, 2002.
Alex Kondratyev and Alexander Taubin. Verification of speed-independent circuits by stg unfoldings. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 64-75, November 1994.
A. Kondratyev, L. Rosenblum, and A. Yakovlev. Signal graphs: A model for designing concurrent logic. In Fayé A. Briggs, editor, Proc. International Conference on Parallel Processing, volume 1, pages 51-54, 1988.
Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, and Alex Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56-62, June 1994. (PostScript)
A. Kondratyev, J. Cortadella, M. Kishinevsky, E. Pastor, O. Roig, and A. Yakovlev. Checking Signal Transition Graph implementability by symbolic BDD traversal. In Proc. European Design and Test Conference, pages 325-332, Paris, France, March 1995.
Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, and Alex Yakovlev. Technology mapping for speed-independent circuits: decomposition and resynthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 240-253. IEEE Computer Society Press, April 1997.
A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. Taubin, and A. Yakovlev. Identifying state coding conflicts in asynchronous system specifications using Petri net unfoldings. In Int. Conf. on Application of Concurrency to System Design, March 1998.
A. Kondratyev, M. Kishinevsky, A. Taubin, J. Cortadella, and L. Lavagno. The use of Petri nets for the design and verification of asynchronous circuits and systems. Journal of Circuits Systems and Computers, 8(1):67-118, 1998.
Alex Kondratyev, Michael Kishinevsky, Alexander Taubin, and Sergei Ten. Analysis of Petri nets by ordering relations in reduced unfoldings. Formal Methods in System Design, 12(1):5-38, January 1998.
Alex Kondratyev, Michael Kishinevsky, and Alex Yakovlev. Hazard-free implementation of speed-independent circuits. IEEE Transactions on Computer-Aided Design, 17(9):749-771, September 1998.
Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, and Alexander Yakovlev. Automatic synthesis and optimization of partially specified asynchronous systems. In Proc. ACM/IEEE Design Automation Conference, pages 110-115, 1999.
Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, and Alexander Yakovlev. Logic decomposition of speed-independent circuits. Proceedings of the IEEE, 87(2):347-362, February 1999.
Alex Kondratyev, Lawrence Neukom, Oriol Roig, Alexander Taubin, and Karl Fant. Checking delay-insensitivity: 10⁴ gates and beyond. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 149-157, April 2002.
Alex Kondratyev, Lief Sorensen, and Amy Streich. Testing of asynchronous designs by inappropriate means. synchronous approach. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 171-180, April 2002. (PDF)
B.-S. Kong and Y.-H. Jun. Set of self-timed latches for high-speed VLSI. IEE Proceedings, Circuits, Devices and Systems, 146(6):341-344, December 1999.
X. Kong and R. Negulescu. Formal verification of pulse-mode circuits. In Proc. of Asia and South Pacific Design Automation Conference, pages 347-352, February 2001.
Xiaohua Kong and Radu Negulescu. Formal verification of peephole optimizations in asynchronous circuits. In Proc. 21st IFIP International Conference on Formal Techniques for Networked and Distributed Systems (FORTE), 2001. (PDF)
X. Kong and R. Negulescu. Bolstering faith in GasP circuits through formal verification. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 113-124. IEEE Computer Society Press, April 2004.
Xiaohua Kong, Radu Negulescu, and Larry Weidong Ying. Refinement-based formal verification of asynchronous wrappers for independently clocked domains in systems on chip. In Proc. 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), September 2001. (PDF)
Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Kiyoshi Oguri, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, and Kouichi Nagami. PCA-1: A fully asynchronous self-reconfigurable LSI. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 54-61. IEEE Computer Society Press, March 2001.
M. van der Korst, A. Peeters, and H. Schols, editors. Design and Implementation of Asynchronous Circuits. Koninklijke Nederlandse Akademie van Wetenschappen, North-Holland, June 1992. Proceedings of workshop Amsterdam, 10-14 November 1991.
Michiel van der Korst. VOICE, a silicon compiler for asynchronous circuits. Technical report, IVO, Eindhoven University of Technology, August 1992.
W. H. F. J. Körver and I. M. Nedelchev. Asynchronous implementation of the SCPP-A counterflow pipeline processor. IEE Proceedings, Computers and Digital Techniques, 143(5):287-294, September 1996.
Odysseas Koufopavlou. AMIED: Asynchronous low-power methodology and implementation of an encryption/decryption system. In Rene van Leuken, Reinder Nouta, and Alexander de Graaf, editors, European Low Power Initiative for Electronic System Design, pages 53-74. Delft Institute of Microelectronics and Submicron Technology, July 2000.
J. Kramer. An ON/OFF transient imager with event-driven, asynchronous read-out. In Proc. International Symposium on Circuits and Systems, volume 2, pages 165-168, 2002.
Ilya V. Krotchkov, Alexander B. Smirnov, and Nikolai A. Starodoubtsev. Verification driven synthesis of asynchronous circuits from STG specification. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 377-386, October 1998.
Milos Krstic and Eckhard Grass. New GALS technique for datapath architectures. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 161-170, September 2003.
W. Kuang, J. S. Yuan, and A. Ejnioui. Supply voltage scalable system design using self-timed circuits. In IEEE Computer Society Symposium on VLSI, February 2003.
Prabhakar Kudva and Venkatesh Akella. A technique for estimating power in self-timed asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 166-175, November 1994.
Prabhakar Kudva and Venkatesh Akella. Testing two-phase transition signalling based self-timed circuits in a synthesis environment. In Proceedings of the 7th International Symposium on High-Level Synthesis, pages 104-111. IEEE Computer Society Press, May 1994.
P. Kudva, G. Gopalakrishnan, and E. Brunvand. Performance analysis and optimization for asynchronous circuits. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
P. Kudva, G. Gopalakrishnan, and V. Akella. High level synthesis of asynchronous circuit targeting state machine controllers. In Asia-Pacific Conference on Hardware Description Languages (APCHDL), pages 605-610, 1995.
Prabhakar Kudva, Ganesh Gopalakrishnan, and Hans Jacobson. A technique for synthesizing distributed burst-mode circuits. In Proc. ACM/IEEE Design Automation Conference, 1996.
Prabhakar Kudva, Ganesh Gopalakrishnan, Hans Jacobson, and Steven M. Nowick. Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes. In Proc. ACM/IEEE Design Automation Conference, 1996.
J. G. Kuhl and S. M. Reddy. A multicode single transition-time state assignment for asynchronous sequential machines. IEEE Transactions on Computers, 27:927-934, October 1978.
S. Y. Kung and R. J. Gal-Ezer. Synchronous versus asynchronous computation in very large scale integrated (VLSI) array processors. In Joel Trimble, editor, Real Time Signal Processing V, volume 341 of Proceedings of SPIE, pages 53-65, May 1982.
I. Kurosawa, H. Nakagawa, M. Aoyagi, M. Maezawa, Y. Kameda, and T. Nanya. A basic circuit for asynchronous superconductive logic using RSFQ gates. In Extended Abstracts of ISEC 95, pages 204-206, September 1995.
I. Kurosawa, H. Nakagawa, M. Aoyagi, M. Maezawa, Y. Kameda, and T. Nanya. A basic circuit for asynchronous superconductive logic using RSFQ gates. Superconductor-Science-Technology, 9(4A):A46-49, April 1996.
R. P. Kurshan, M. Merritt, A. Orda, and S. R. Sachs. Modelling asynchrony with a synchronous model. In Proc. International Workshop on Computer Aided Verification, 1995.
Masashi Kuwako and Takashi Nanya. Timing-reliability evaluation of asynchronous circuits based on different delay models. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 22-31, November 1994.
Yong-Jin Kwon and S. Yajima. Minimum single transition-time assignment for asynchronous sequential circuits using BDD. Transactions of the Information Processing Society of Japan, 35(2):352-357, February 1994.
G. Lacroix, P. Marchegay, and G. Piel. Comments on `the anomalous behavior of flip-flops in synchronizer circuits'. IEEE Transactions on Computers, 31(1):77-78, January 1982. See: Fleischhammer 1979.
M. Ladd and W. P. Birmingham. Synthesis of multiple-input change asynchronous finite state machines. In Proc. ACM/IEEE Design Automation Conference, pages 309-314, 1991.
M. Laiho and O. Vianio. A full-custom self-timed DSP processor implementation. In Proc. European Solid-State Circuits Conference (ESSCIRC), September 1997. Poster.
P. N. Lam and H. F. Li. Hierarchical design of delay-insensitive systems. IEE Proceedings, Computers and Digital Techniques, E-137(1):41-56, January 1990.
P. N. Lam, Hon F. Li, and S. C. Leung. Optimization of state encoding in distributed circuits. IEEE Transactions on Computer-Aided Design, 13(5):581-588, May 1994.
H. Lampinen and O. Vainio. Circuit design for current-sensing completion detection. In Proc. International Symposium on Circuits and Systems, volume 2, pages 185-188, June 1998.
T. Landan. Asynchronous timing in logic systems. Digital Processes, pages 157-162, 1976.
C. H. Lau, D. Renshaw, and J. Mavor. Data-flow approach to self-timed logic in VLSI. In Proc. International Symposium on Circuits and Systems, pages 479-482, June 1988.
C. H. Lau, D. Renshaw, and J. Mavor. A self-timed wavefront array multiplier. In Proc. International Symposium on Circuits and Systems, pages 138-141, 1989.
C. H. Lau. Self: a self-timed system design technique. Electronics Letters, 23(6):269-270, March 1987.
L. Lavagno and A. Sangiovanni-Vincentelli. Linear programming for optimum hazard elimination in asynchronous circuits. In Proc. International Conf. Computer Design (ICCD), pages 275-278. IEEE Computer Society Press, October 1992.
L. Lavagno and A. Sangiovanni-Vincentelli. Automated synthesis of asynchronous interface circuits. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 107-121. Elsevier Science Publishers, 1993.
Luciano Lavagno and Alberto Sangiovanni-Vincentelli. Algorithms for Synthesis and Testing of Asynchronous Circuits. Kluwer Academic Publishers, 1993.
Luciano Lavagno, Kurt Keutzer, and Alberto Sangiovanni-Vincentelli. Algorithms for synthesis of hazard-free asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 302-308. IEEE Computer Society Press, 1991.
Luciano Lavagno, Kurt Keutzer, and Alberto Sangiovanni-Vincentelli. Synthesis of verifiably hazard-free asynchronous control circuits. In Advanced Research in VLSI, pages 87-102. MIT Press, 1991.
L. Lavagno, C. Moon, R. Brayton, and A. Sangiovanni-Vincentelli. Solving the state assignment problem for signal transition graphs. In Proc. ACM/IEEE Design Automation Conference, pages 568-572. IEEE Computer Society Press, June 1992.
Luciano Lavagno, Michael Kishinevsky, and Antonio Lioy. Testing redundant asynchronous circuits. Technical Report ID-TR:1993-124, Dept. of Comp. Science, Technical University of Denmark, 1993.
L. Lavagno, N. Shenoy, and A. Sangiovanni-Vincentelli. Linear programming for hazard elimination in asynchronous circuits. Journal of VLSI Signal Processing, 7(1/2):137-160, February 1994.
Luciano Lavagno, Michael Kishinevsky, and Antonio Lioy. Testing redundant asynchronous circuits by variable phase splitting. In Proc. European Design Automation Conference (EURO-DAC), pages 328-333. IEEE Computer Society Press, September 1994. (PostScript)
Luciano Lavagno, Kurt Keutzer, and Alberto Sangiovanni-Vincentelli. Synthesis of hazard-free asynchronous circuits with bounded wire delays. IEEE Transactions on Computer-Aided Design, 14(1):61-86, January 1995.
Luciano Lavagno, Cho W. Moon, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. An efficient heuristic procedure for solving the state assignment problem for event-based specifications. IEEE Transactions on Computer-Aided Design, 14(1):45-60, January 1995.
Luciano Lavagno. Synthesis and Testing of Bounded Wire Delay Asynchronous Circuits from Signal Transition Graphs. PhD thesis, U.C. Berkeley, November 1992. Technical report UCB/ERL M92/140. (PostScript)
Y. Leblebici, H. Özdemir, A. Kepkep, and U. Çilingiroglu. A compact high-speed (31,5) parallel counter circuit based on capacitive threshold-logic gates. IEEE Journal of Solid-State Circuits, 31(8):1177-1183, August 1996.
KiJong Lee and Kiyoung Choi. Self-timed divider based on RSD number system. IEEE Transactions on VLSI Systems, 4(2):292-295, June 1996.
Trevor W. S. Lee, Mark R. Greenstreet, and Carl-Johan Seger. Automatic verification of asynchronous circuits. IEEE Design & Test of Computers, 12(1):24-31, Spring 1995.
Jeong-Gun Lee, Euiseok Kim, and Dong-Ik Lee. Imprecise data computation for high performance asynchronous processors. In Proc. of Asia and South Pacific Design Automation Conference, pages 261-266, February 2001.
J. Lee, F. Peper, S. Adachi, K. Morita, and S. Mashiko. Reversible computation in asynchronous cellular automata. In Proc. 3rd Conf. on Unconventional Models of Computation (UCM02), pages 220-220. Springer-Verlag, 2002.
Tak Kwan Lee. A General Approach to Performance Analysis and Optimization of Asynchronous Circuits. PhD thesis, California Institute of Technology, 1995. Technical report CS-TR-95-07. (PostScript)
I. Lemberski and M. Josephs. Optimal two-level delay-insensitive implementation of logic functions. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2451 of Lecture Notes in Computer Science, September 2002.
I. Lemberski. Internal state assignment for two-level hazard-free asynchronous implementation. In P. Garda, editor, Proc. European Solid-State Circuits Conference (ESSCIRC), pages 414-417, September 1995.
S. C. Leung and Hon F. Li. A syntax-directed translation for the synthesis of delay-insensitive circuits. IEEE Transactions on VLSI Systems, 2(2):196-210, June 1994.
S. C. Leung and H. F. Li. On the realizability and synthesis of delay-insensitive behaviors. IEEE Transactions on Computer-Aided Design, 14(7):833-848, July 1995.
S. C. Leung. Synthesis of Delay-Insensitive Circuits from Graph-Theoretic Specifications. PhD thesis, Concordia University, Montreal, 1993.
Lavi A. Lev et al. A 64-b microprocessor with multimedia support. IEEE Journal of Solid-State Circuits, 30(11):1227-1238, November 1995.
M. Lewis and L. Brackenbury. An instruction buffer for a low-power DSP. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 176-186. IEEE Computer Society Press, April 2000.
M. Lewis and L. Brackenbury. Exploiting typical DSP data access patterns and asynchrony for a low power multiported register bank. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 4-14. IEEE Computer Society Press, March 2001.
M. Lewis, J. D. Garside, and L. Brackenbury. Reconfigurable latch controllers for low power asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 27-35, April 1999.
Jon Lexau, John Will, and Ian Jones. EM emissions of an asynchronous test chip. In Proceedings of the 14th International Zurich Symposium and Technical Exhibition of Electromagnetic Compatibility, pages 579-584. Communication Technology Laboratory of the Swiss Federal Institute of Technology Zurich, February 2001.
Tao Li and Lee A. Hollaar. On the testability of the direct implementation of asynchronous circuits. In Paul Penfield, editor, Advanced Research in VLSI, January 1984.
S. H. Li and C. A. Zukowski. Application of dynamic power supply scaling in a low-energy ATM interface. In Proc. International Symposium on Circuits and Systems, volume 5, pages 745-748, May 2000.
H. F. Li, S. C. Leung, and P. N. Lam. Synthesis of delay-insensitive circuits by refinement into atomic threads. In Proc. International Conf. Computer Design (ICCD), pages 180-186. IEEE Computer Society Press, October 1991.
H. F. Li, S. C. Leung, and P. N. Lam. Optimised synthesis of delay-insensitive circuits using time-sharing. IEE Proceedings, Computers and Digital Techniques, 141(2):111-118, 1994.
Yee William Li, George Patounakis, Anup Jose, K. L. Shepard, and S. M. Nowick. Asynchronous datapath with software-controlled on-chip adaptive voltage scaling for multirate signal processing applications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 216-225. IEEE Computer Society Press, May 2003.
S. H. Li. Methodologies for efficient asynchronous circuits design. In Proceedings of The Twenty-Ninth Southeastern Symposium on System Theory, pages 154-158, March 1997.
Xiaofeng Liao and Jen-Shiun Chiang. The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider. In Proc. International Symposium on Circuits and Systems, 1998.
Xiaofeng Liao and Jen-Shiun Chiang. A novel asynchronous control unit and the application to a pipelined multiplier. In Proc. International Symposium on Circuits and Systems, 1998.
Armin Liebchen and Ganesh Gopalakrishnan. Dynamic reordering of high latency transactions using a modified pipeline. In Proc. International Conf. Computer Design (ICCD), pages 336-340. IEEE Computer Society Press, October 1992.
Michael J. Liebelt and Neil Burgess. Detecting exitory stuck-at faults in semimodular asynchronous circuits. IEEE Transactions on Computers, 48(4):442-448, April 1999.
Michiel Ligthart, Karl Fant, Ross Smith, Alexander Taubin, and Alex Kondratyev. Asynchronous design using commercial HDL synthesis tools. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 114-125. IEEE Computer Society Press, April 2000.
Pasi Liljeberg, Juha Plosila, and Jouni Isoaho. Self-timed design concepts for IP based systems. In Proc. of IP 2000 System-on-chip Conference, pages 153-166, March 2000.
Pasi Liljeberg, Juha Plosila, and Jouni Isoaho. Synchronous/asynchronous interface unit for IP based SoC systems. In Proc. of the 18th IEEE NORCHIP conference, pages 160-165, November 2000.
Pasi Liljeberg, Juha Plosila, and Jouni Isoaho. Asynchronous interface for locally clocked modules in ULSI systems. In Proc. International Symposium on Circuits and Systems, volume 4, pages 170-173, 2001. (PDF)
W. Lim. Design methodology for stoppable clock systems. IEE Proceedings, Computers and Digital Techniques, 133(1):65-69, January 1986.
Bill Lin and Srinivas Devadas. Synthesis of hazard-free multi-level logic under multiple-input changes from binary decision diagrams. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 542-549, November 1994.
Bill Lin and Srinivas Devadas. Synthesis of hazard-free multilevel logic under multi-input changes from binary decision diagrams. IEEE Transactions on Computer-Aided Design, 14(8):974-985, August 1995.
K.-J. Lin and C.-S. Lin. Automatic synthesis of asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 296-301. IEEE Computer Society Press, 1991.
K.-J. Lin and C.-S. Lin. On the verification of state-coding in STGs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 118-122. IEEE Computer Society Press, November 1992.
K.-J. Lin and C.-S. Lin. A realization algorithm of asynchronous circuits from STG. In Proc. European Conference on Design Automation (EDAC), pages 322-326. IEEE Computer Society Press, 1992.
K.-J. Lin and C.-S. Lin. Removing CSC violations in asynchronous circuits by delay padding. IEE Proceedings, Computers and Digital Techniques, 143(6):413-420, November 1996.
Bill Lin, Chantal Ykman-Couvreur, and Peter Vanbekbergen. A general state graph transformation framework for asynchronous synthesis. In Proc. European Design Automation Conference (EURO-DAC), pages 448-453. IEEE Computer Society Press, September 1994.
Kuan-Jen Lin, Jih-Wen Kuo, and Chen-Shang Lin. Direct synthesis of hazard-free asynchronous circuits from STGs based on lock relation and MG-decomposition approach. In Proc. European Design and Test Conference, pages 178-183. IEEE Computer Society Press, 1994.
Bill Lin, Gjalt de Jong, and Tilman Kolks. Hierarchical optimization of asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, June 1995.
Kuan-Jen Lin, Chi-Wen Kuo, and Chen-Shang Lin. Synthesis of hazard-free asynchronous circuits based on characteristic graph. IEEE Transactions on Computers, 46(11):1246-1263, November 1997.
Yu Sheng Lin, Shan Chieh Yang, Su Jen Fang, and C. B. Shung. VLSI design of a priority arbitrator for shared buffer ATM switches. In Proc. International Symposium on Circuits and Systems, volume 4, pages 2785-2788, June 1997.
R. Lin. Shift switching with domino logic: asynchronous VLSI comparator schemes. In Proc. International Conference on VLSI Design, pages 520-522. IEEE Computer Society Press, January 1997.
Daniel H. Linder and James C. Harden. Phased logic: Supporting the synchronous design paradigm with delay-insensitive circuitry. IEEE Transactions on Computers, 45(9):1031-1044, September 1996.
Daniel H. Linder. Phased Logic: A Design Methodology for Delay-Insensitive, Synchronous Circuitry. PhD thesis, Mississippi State Univ., 1994.
Andrew Lines. Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs. In Proceedings of the 11th Symposium on High Performance Interconnects, pages 2-9, August 2003.
J. B. Lipsher and K. Maheswaran. A 4-bit asynchronous pipelined multiplier in the Xilinx 4000 series FPGA. Technical report, University of California, Davis, 1994. (PostScript)
Jonathan Brian Lipsher. The asynchronous discrete cosine transform processor core. Master's thesis, University of California, Davis, 1994. (PostScript)
R. J. Lipton, R. E. Miller, and L. Snyder. Synchronization and computing capabilities of linear asynchronous structures. In Proc. 16th Annual Symposium on Foundations of Computer Science, pages 19-28, October 1975.
P. F. Lister. Design methodology for self-timed VLSI systems. IEE Proceedings, Computers and Digital Techniques, 132(1):25-32, January 1985.
Ying Liu and Graham Birtwistle. Specifying and property checking the AMULET1 address interface. In Designing Correct Circuits, 1996.
C. N. Liu. A state variable assignment method for asynchronous sequential switching circuits. Journal of the ACM, 10:209-216, 1963.
Ying Liu. Reasoning about asynchronous designs in CCS. Master's thesis, Dept. of Electrical and Computer Engineering, University of Calgary, 1992.
J. Liu. Arithmetic and control components for an asynchronous microprocessor. PhD thesis, Department of Computer Science, University of Manchester, 1997.
D. W. Lloyd and J. D. Garside. A practical comparison of asynchronous design styles. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 36-45. IEEE Computer Society Press, March 2001.
D. Lloyd and S. Jones. Improved self-timed circuit design method. Electronics Letters, 28(5):492-493, February 1992.
Lee Lloyd, Alex V. Yakovlev, Enric Pastor, and Albert M. Koelmans. Estimation of power consumption in asynchronous logic as derived from graph based circuit representations. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 367-376, October 1998.
D. W. Lloyd, J. D. Garside, and D. A. Gilbert. Memory faults in asynchronous microprocessors. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 71-80, April 1999.
Sonia López, Óscar Garnica, Ignacio Hidalgo, Juan Lanchares, and Román Hermida. Power-consumption reduction in asynchronous circuits using delay path unequalization. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 151-160, September 2003.
Shih-Lien Lu and Lalit Merani. Micro data flow. In 4th Annual IEEE International ASIC Conference and Exhibit, 1992.
S.L. Lu. Improved design of CMOS multiple-input Muller-C-elements. Electronics Letters, 29(19), September 1993.
Shih-Lien Lu. Implementation of micropipelines in enable/disable CMOS differential logic. IEEE Transactions on VLSI Systems, 3(2):338-341, June 1995.
S. Lubkin. Asynchronous circuits in digital computers. Mathematical Tables and other Aids to Computation, pages 238-241, October 1952.
P. G. Lucassen and J. T. Udding. High-level design and verification of an asynchronous queue controller. In Power and Timing Modeling, Optimization and Simulation (PATMOS), October 1995.
P. G. Lucassen and J. T. Udding. On the correctness of the Sproull counterflow pipeline processor. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
Paul G. Lucassen, Indra Polak, and Jan Tijmen Udding. Normal form in DI-algebra with recursion. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 167-174. IEEE Computer Society Press, April 1997.
Paul G. Lucassen. A Denotational Model and Composition Theorems for a Calculus of Delay-Insensitive Specifications. PhD thesis, Dept. of C.S., Univ. of Groningen, The Netherlands, May 1994.
G. Lüttgen and W. Vogler. A faster-than relation for asynchronous processes. In Proceedings of the 12th International Conference on Concurrency Theory (CONCUR91), volume 2154 of Lecture Notes in Computer Science, pages 262-276. Springer-Verlag, 2001.
J. W. J. M., M. R. C. M. Berkelaar, C. A. J. van Eijk, and M. A. J. Kolsteren. An efficient divide and conquer algorithm for exact hazard free logic minimization. In Proc. Design, Automation and Test in Europe (DATE), pages 749-754, April 1998.
A. Kondratyev M. Kishinevsky, J. Cortadella and L. Lavagno. Asynchronous interface specification, analysis and synthesis. Technical report, Universitat Politècnica de Catalunya, March 1998. (PostScript)
R. P. Mackey, J. J. Rodriguez, J. D. Carothers, and S. B. K. Vrudhula. A single-chip, asynchronous echo canceller for high-speed data communication. In W. A. Cook, R. A. Hull, and C. Traver, editors, Proceedings of Eighth International Application Specific Integrated Circuits Conference, pages 181-184, September 1995.
R. P. Mackey, J. J. Rodriguez, J. D. Carothers, and S. B. K. Vrudhula. Asynchronous VLSI architecture for adaptive echo cancellation. Electronics Letters, 32(8):710-711, 1996.
A. Madalinski, A. Bystrov, V. Khomenko, and A. Yakovlev. Visualization and resolution of coding conflicts in asynchronous circuit design. In Proc. Design, Automation and Test in Europe (DATE). IEEE Computer Society Press, March 2003.
J. K. Madsen and P. S. Lassen. A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI. IEEE Journal of Solid-State Circuits, 31(10):1400-1405, 1996.
O. Maevsky, D.J. Kinniment, A. Yakovlev, and A. Bystrov. Analysis of the oscillation problem in tri-flops. In Proc. International Symposium on Circuits and Systems, volume 1, pages 381-384, 2002.
M. Maezawa, I. Kurosawa, Y. Kameda, and T. Nanya. Pulse-driven dual-rail logic gate family based on rapid single flux quantum (RSFQ) devices for asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
M. Maezawa, I. Kurosawa, M. Aoyagi, H. Nakagawa, Y. Kameda, and T. Nanya. Rapid single-flux-quantum dual-rail logic for asynchronous circuits. IEEE Transactions on Applied Superconductivity, 7(2):2705-2708, June 1997.
Gyula Magó. Asynchronous sequential circuits with (2,1) type state assignments. In Annual Symposium on Switching and Automata Theory, pages 109-113. IEEE Computer Society Press, 1970.
G. Magó. Realization methods for asynchronous sequential circuits. IEEE Transactions on Computers, C-20(3):290-297, March 1971.
K. Maheswaran and V. Akella. Hazard-free implementation of the self-timed cell set for the Xilinx 4000 series FPGA. Technical report, University of California, Davis, 1994. (PostScript)
K. Maheswaran and J. B. Lipsher. A cell set for self-timed design using Xilinx XC4000 series FPGA. Technical report, University of California, Davis, 1994. (PostScript)
K. Maheswaran. Implementing self-timed circuits in field programmable gate arrays. Master's thesis, University of California, Davis, 1994.
Rudolf H. Mak and Mark B. Josephs. Proceedings of ACiD-WG/EXACT workshop on asynchronous data processing. Technical Report EXACT/D.2/EUT/m6/D2, Dept. of Math. and C.S., Eindhoven Univ. of Technology, December 1992.
Rudolf H. Mak. Design and performance analysis of buffers: a constructive approach. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 137-148, April 2002.
Gary K. Maki and Kristen Q. Chen. Partition algebraic design of asynchronous sequential circuits. In Proc. 1st International Conference on ASIC, pages 313-315, Beijing, China, October 1994.
G. K. Maki and J. H. Tracy. A state assignment procedure for asynchronous sequential circuits. IEEE Transactions on Computers, 20:666-668, June 1971.
G. K. Maki, J. H. Tracy, and R. J. Smith. Generation of design equations in asynchronous sequential circuits. IEEE Transactions on Computers, 18:467-472, May 1969.
Yonatan Malachi and Susan S. Owicki. Temporal specifications of self-timed systems. In H. T. Kung, Bob Sproull, and Guy Steele, editors, VLSI Systems and Computations, pages 203-212. Computer Science Press, 1981.
Willem C. Mallon and Jan Tijmen Udding. Construction of an operational semantics for DI-algebra. Technical Report CSN 9710, Dept. of Comp. Science, Univ. of Groningen, 1997.
Willem C. Mallon and Jan Tijmen Udding. Using metrics for proof rules for recursively defined delay-insensitive specifications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 175-183. IEEE Computer Society Press, April 1997.
Willem C. Mallon and Jan Tijmen Udding. Building finite automatons from DI specifications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 184-193, 1998.
W. C. Mallon, J. T. Udding, and T. Verhoeff. Analysis and applications of the XDI model. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 231-242, April 1999. (PDF)
Willem C. Mallon. On directed transformations of delay-insensitive specifications, alternations and dynamic nondeterminism. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 12-22, April 2000.
Willem C. Mallon. Theories and Tools for the Design of Delay-Insensitive Communicating Processes. PhD thesis, Dept. of Comp. Science, Univ. of Groningen, 2000.
R. Männer. Metastable states in asynchronous digital systems - avoidable or unavoidable. Microelectronics and Reliability, 28(2):295-307, 1988.
R. Manohar and A. J. Martin. Quasi-delay-insensitive circuits are Turing complete. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
Rajit Manohar and Alain J. Martin. Slack elasticity in concurrent computing. In J. Jeuring, editor, Proc. 4th International Conference on the Mathematics of Program Construction, volume 1422 of Lecture Notes in Computer Science, pages 272-285, 1998. (PostScript)
Rajit Manohar and José A. Tierno. Asynchronous parallel prefix computation. IEEE Transactions on Computer-Aided Design, 47(11):1244-1252, November 1998. An earlier version is available as Caltech technical report CS-TR-96-20. (PostScript)
Rajit Manohar, Tak-Kwan Lee, and Alain J. Martin. Projection: A synthesis technique for concurrent systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 125-134, April 1999. (PostScript)
Rajid Manohar, Mika Nyström, and Alain J. Martin. Precise exceptions in asynchronous processors. In Advanced Research in VLSI, pages 16-28, March 2001.
Rajit Manohar. The Impact of Asynchrony on Computer Architecture. PhD thesis, California Institute of Technology, 1998. Available as Caltech technical report CS-TR-98-12.
Rajid Manohar. An analysis of reshuffled handshaking expansions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 96-105. IEEE Computer Society Press, March 2001.
R. Mariani, F. Pessolano, and R. Saletti. A new CMOS ternary logic for low-power low-voltage circuits. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 1997.
R. Mariani, R. Roncella, R. Saletti, and P. Terreni. On the realisation of delay-insensitive asynchronous circuits with CMOS ternary logic. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 54-62. IEEE Computer Society Press, April 1997.
R. Mariani, R. Roncella, R. Saletti, and P. Terreni. A useful application of CMOS ternary logic to the realisation of asynchronous circuits. In Proc. IEEE International Symposium on Multiple-Valued Logic, pages 203-208. IEEE Computer Society Press, 1997.
Leonard R. Marino. The effect of asynchronous inputs on sequential network reliability. IEEE Transactions on Computers, 26:1082-1090, 1977.
Leonard R. Marino. General theory of metastable operation. IEEE Transactions on Computers, C-30(2):107-115, February 1981.
J. Alves Marques and A. Cunha. Clocking of VLSI circuits. In B. Randell and P. C. Treleaven, editors, VLSI Architecture, chapter 15, pages 165-178. Prentice-Hall, 1983.
Alan Marshall, Bill Coates, and Polly Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8-21, 1994. (PostScript)
Alain J. Martin and Pieter J. Hazewindus. Testing delay-insensitive circuits. In Carlo H. Séquin, editor, Advanced Research in VLSI, pages 118-132. MIT Press, 1991.
Alain J. Martin, Steven M. Burns, T. K. Lee, Drazen Borkovic, and Pieter J. Hazewindus. The design of an asynchronous microprocessor. In Charles L. Seitz, editor, Advanced Research in VLSI, pages 351-373. MIT Press, 1989.
Alain J. Martin, Steven M. Burns, T. K. Lee, Drazen Borkovic, and Pieter J. Hazewindus. The first asynchronous microprocessor: the test results. Computer Architecture News, 17(4):95-110, June 1989.
Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul Pénzes, Robert Southworth, and Uri Cummings. The design of an asynchronous MIPS R3000 microprocessor. In Advanced Research in VLSI, pages 164-181, September 1997. (PostScript) (PDF)
Alain J. Martin, Mika Nyström, Paul Pénzes, and Catherine Wong. Speed and energy performance of an asynchronous MIPS R3000 microprocessor. Technical Report CSTR:2001.012, California Institute of Technology, 2001.
Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, and Ahmet Tura. The lutonium: A sub-nanojoule asynchronous 8051 microcontroller. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 14-23. IEEE Computer Society Press, May 2003.
Alain J. Martin, Mika Nyström, and Catherine G. Wong. Three generations of asynchronous microprocessors. IEEE Design & Test of Computers, 20(6):9-17, 2003.
Alain J. Martin. A delay-insensitive fair arbiter. Technical Report 5193:TR:85, California Institute of Technology, 1985.
Alain J. Martin. The design of a self-timed circuit for distributed mutual exclusion. In Henry Fuchs, editor, Proceedings of the 1985 Chapel Hill Conference on VLSI, pages 245-260. Computer Science Press, 1985.
Alain J. Martin. The probe: An addition to communication primitives. Information Processing Letters, 20(3):125-130, 1985. Erratum: IPL 21(2):107, 1985.
Alain J. Martin. Compiling communicating processes into delay-insensitive VLSI circuits. Distributed Computing, 1(4):226-234, 1986.
Alain J. Martin. On Seitz's arbiter. Technical Report 5212:TR:86, Caltech Computer Science, 1986.
Alain J. Martin. Self-timed FIFO: An exercise in compiling programs into VLSI circuits. In D. Borrione, editor, From HDL Descriptions to Guaranteed Correct Circuit Designs, pages 133-153. Elsevier Science Publishers, 1986.
Alain J. Martin. A synthesis method for self-timed VLSI circuits. In Proc. International Conf. Computer Design (ICCD), pages 224-229, Rye Brook, NY, 1987. IEEE Computer Society Press.
Alain J. Martin. The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation. In M. Leeser and G. Brown, editors, Hardware Specification, Verification and Synthesis: Mathematical Aspects, volume 408 of Lecture Notes in Computer Science, pages 244-259. Springer-Verlag, 1989.
Alain J. Martin. Formal program transformations for VLSI circuit synthesis. In Edsger W. Dijkstra, editor, Formal Development of Programs and Proofs, UT Year of Programming Series, pages 59-80. Addison-Wesley, 1989.
Alain J. Martin. The limitations to delay-insensitivity in asynchronous circuits. In William J. Dally, editor, Advanced Research in VLSI, pages 263-278. MIT Press, 1990.
Alain J. Martin. Programming in VLSI: From communicating processes to delay-insensitive circuits. In C. A. R. Hoare, editor, Developments in Concurrency and Communication, UT Year of Programming Series, pages 1-64. Addison-Wesley, 1990.
Alain J. Martin. Synthesis of asynchronous VLSI circuits. In J. Straunstrup, editor, Formal Methods for VLSI Design, chapter 6, pages 237-283. North-Holland, 1990.
Alain J. Martin. Synthesis of asynchronous VLSI circuits. Course Notes, VLSI91, Edinburgh, August 1991.
Alain J. Martin. Asynchronous datapaths and the design of an asynchronous adder. Formal Methods in System Design, 1(1):119-137, July 1992.
Alain J. Martin. Tomorrow's digital hardware will be asynchronous and verified. In J. van Leeuwen, editor, Information Processing 92, Vol. I: Algorithms, Software, Architecture, volume A-12 of IFIP Transactions, pages 684-695. Elsevier Science Publishers, 1992.
Alain J. Martin. Synthesis of asynchronous VLSI circuits. Technical Report Caltech-CS-TR-93-28, California Institute of Technology, 1993. (PostScript)
Alain J. Martin. Remarks on low-power advantages of asynchronous circuits. In Proc. European Solid-State Circuits Conference (ESSCIRC), 1998. (PostScript)
Alain J. Martin. An asynchronous approach to energy-efficient computing and communication. In Proc. SSGRR 2000, International Conference on Advances in Infrastructure for Electronic Business, Science, and Education on the Internet, August 2000. (PostScript)
Alain J. Martin. Towards an energy complexity of computation. Information Processing Letters, 77:181-187, 2001. (PostScript)
Steve Masteller and Lief Sorenson. Cycle decomposition in NCL. IEEE Design & Test of Computers, 20(6):38-43, 2003.
Sanu Mathew and Ramalingam Sridhar. Data-driven self-timed differential cascode voltage switch logic. In Proc. International Symposium on Circuits and Systems, pages 165-168, June 1998.
Gensoh Matsubara and Nobuhiro Ide. A low power zero-overhead self-timed division and square root unit combining a single-rail static circuit with a dual-rail dynamic circuit. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 198-209. IEEE Computer Society Press, April 1997.
P. Maurine, J.B. Rigaud, F. Bouesse, G. Sicard, and M. Renaudin. Static implementation of QDI asynchronous primitives. In Jorge Juan Chico and Enrico Macii, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2799 of Lecture Notes in Computer Science, pages 181-191, September 2003.
Clive Maxfield. To be or not to be asynchronous; that is the question. EDN, pages 157-173, Dec 7 1995.
Anthony J. McAuley. Dynamic asynchronous logic for high-speed CMOS systems. IEEE Journal of Solid-State Circuits, 27(3):382-388, March 1992.
Anthony J. McAuley. Four state asynchronous architectures. IEEE Transactions on Computers, 41(2):129-142, February 1992.
Kenneth McMillan. Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits. In G. v. Bochman and D. K. Probst, editors, Proc. International Workshop on Computer Aided Verification, volume 663 of Lecture Notes in Computer Science, pages 164-177. Springer-Verlag, 1992.
K. L. McMillan. Trace theoretic verification of asynchronous circuits using unfoldings. In Proc. International Workshop on Computer Aided Verification, 1995.
R. Mehra and J. D. Garside. A cache line fill circuit for a micropipelined, asynchronous microprocessor. IEEE Technical Committee on Computer Architecture Newsletter, October 1995. (PostScript)
R. Mehra. Micropipelined cache design strategies for an asynchronous microprocessor. Master's thesis, Department of Computer Science, University of Manchester, 1992. (PostScript)
E. Meijer. Hazard algebra and the design of asynchronous automata. In Proc. of the 1992 Glasgow workshop on Functional Programming, pages 166-177, 1992.
T. Meincke, A. Hemani, S. Kumar, P. Ellervee, J. öberg, T. Olsson, P. Nilsson, D. Lindqvist, and H. Tenhunen. Globally asynchronous locally synchronous architecture for large high-performance ASICs. In Proc. International Symposium on Circuits and Systems, 1999.
Michael Mendler and Terry Stroup. Newtonian arbiters cannot be proven correct. Formal Methods in System Design, 3(3), December 1993.
Teresa H. Meng and Sharad Malik, editors. Asynchronous Circuit Design for VLSI Signal Processing. Kluwer Academic Publishers, 1994. Reprinted from Journal of VLSI Signal Processing, 7:1-2.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. A synthesis method for self-timed VLSI circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 514-517, 1987.
T. H.-Y. Meng, G. M. Jacobs, R. W. Brodersen, and D. G. Messerschmitt. Asynchronous processor design for digital signal processing. In International Conference on Acoustics, Speech, and Signal Processing (ICASSP), volume 4, pages 2013-2016, 1988.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. Implementation of high sampling rate adaptive filters using asynchronous design techniques. In Robert W. Brodersen and Howard S. Moscovitz, editors, VLSI Signal Processing, III, chapter 20. IEEE Press, 1988.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. Automatic synthesis of asynchronous circuits from high-level specifications. IEEE Transactions on Computer-Aided Design, 8(11):1185-1205, November 1989.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. A clock-free chip set for high-sampling rate adaptive filters. Journal of VLSI Signal Processing, 1(4):345-365, 1990.
Teresa H.-Y. Meng, Robert W. Brodersen, and David G. Messerschmitt. Asynchronous design for programmable digital signal processors. IEEE Transactions on Signal Processing, 39(4):939-952, April 1991.
Teresa H.-Y. Meng. Asynchronous Design for Digital Signal Processing Architectures. PhD thesis, UC Berkeley, 1988.
Teresa H.-Y. Meng. Synchronization Design for Digital Systems. Kluwer Academic Publishers, 1991. Contributions by David Messerschmitt, Steven Nowick, and David Dill.
E. G. Mercer and C. J. Myers. Stochastic cycle period analysis in timed circuits. In Proc. International Symposium on Circuits and Systems, pages 172-175, 2000.
R. E. Miller. An introduction to speed independent circuit theory. In Proceedings of the Second Annual Symposium and Papers from the First Annual Symposium on Switching Circuit Theory and Logical Design, pages 87-93, October 1961.
R. E. Miller. A survey of asynchronous logic: Comparing various definitions and models for asynchronous switching circuits. In Proceedings of the Fourth Annual Symposium on Switching Circuit Theory and Logical Design, pages 149-152, October 1961.
R. E. Miller. Combinational Circuits, volume 1 of Switching Theory. John Wiley & Sons, 1965.
R. E. Miller. Sequential Circuits and Machines, volume 2 of Switching Theory. John Wiley & Sons, 1965.
Peter H. Mills and J. Dean Brock. A partial order characterization of delay-insensitive circuits. In D. A. Edwards, editor, Proceedings of the IFIP TC-10 Conference on Design Methodologies for VLSI and Computer Architecture, Pisa, Italy, Sept. 1988, 1989. North-Holland.
Robin Milner. Communication and Concurrency. Prentice-Hall, 1989.
Tse Ming-Chi. ASYNMPU: A fully asynchronous microprocessor. Master's thesis, Hong Kong Polytechnic University, 1999.
Yogesh Mishra, S. D. Sherlekar, and G. Venkatesh. Path breaker: A tool for the optimal design of speed independent asynchronous controllers. In Proc. European Design Automation Conference (EURO-DAC), pages 2-8, Hamburg, Germany, September 1992. IEEE Computer Society Press.
David Misunas. Petri nets and speed independent design. Communications of the ACM, 16(8):474-481, August 1973.
Ian Mitchell and Mark R. Greenstreet. Proving Newtonian arbiters correct, almost surely. In Designing Correct Circuits, 1996.
T. Miyamoto and S. Kumagai. An efficient algorithm for deriving logic functions of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
T. Miyamoto and S. Kumagai. On deriving logic functions of asynchronous circuits by STG unfoldings. IEICE Transactions on Information and Systems, E80-D(3):336-343, March 1997.
S. Mohammadi, F. Devos, D. Dulac, and A. Merigot. Current-sensing device for completion detection. International Journal of Electronics, 85(3):337-344, September 1998.
S. Mohammadi, S. Furber, and J. Garside. Designing robust asynchronous circuit components. IEE Proceedings, Circuits, Devices and Systems, 150(5):161-166, June 2003.
Pedro A. Molina and Peter Y.K. Cheung. A quasi delay-insensitive bus proposal for asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 126-139. IEEE Computer Society Press, April 1997.
Pedro A. Molina, P. Y. K. Cheung, and David S. Bormann. Quasi delay-insensitive bus for fully asynchronous systems. In Proc. International Symposium on Circuits and Systems, volume 4, pages 189-192, May 1996.
Pedro A. Molina. The Design of a Delay-Insensitive Bus Architecture using Handshake Circuits. PhD thesis, Imperial College of Science, University of London, UK, 1997.
Jesper Møller, Henrik Hulgaard, and Henrik Reif Andersen. Timed verification of asynchronous circuits. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 274-312. Springer-Verlag, 2002.
Charles E. Molnar and Ting-Pien Fang. Synthesis of reliable speed-independent circuit modules: I. general method for specification of module-environment interaction and derivation of a circuit realization. Technical Memorandum 297, Computer Systems Laboratory, Institute for Biomedical Computing, Washington Univ., St. Louis, MO, 1983.
Charles E. Molnar and Ian W. Jones. Simple circuits that work for complicated reasons. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 138-149. IEEE Computer Society Press, April 2000.
C. Molnar and H. Schols. The design problem SCPP-A. Technical Report SML-97:0538, SUN Microsystems Laboratories, October 1997.
Charles E. Molnar, Ting-Pien Fang, and Frederick U. Rosenberger. Synthesis of delay-insensitive modules. In Henry Fuchs, editor, 1985 Chapel Hill Conference on Very Large Scale Integration, pages 67-86. Computer Science Press, 1985.
Charles E. Molnar, Ian W. Jones, Bill Coates, and Jon Lexau. A FIFO ring oscillator performance experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 279-289. IEEE Computer Society Press, April 1997.
Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau, Scott M. Fairbanks, and Ivan E. Sutherland. Two FIFO ring performance experiments. Proceedings of the IEEE, 87(2):297-307, February 1999.
Charles E. Molnar. Introduction to asynchronous systems. In Proceedings New Frontiers in Computer Science Conference, pages 83-93, Santa Monica: Citicorp/TTI, March 1986.
J. A. Montiel-Nelson and S. Nooshabadi. Architecture and design of a very fast real time delay insensitive asynchronous morphological processor in GaAs. In Proceedings of Digital Processing Applications (TENCON '96), volume 1, pages 363-370, 1996.
J. A. Montiel-Nelson and S. V. Nooshabadi. High performance asynchronous FIR filter design in GaAs. IEE Proceedings, Circuits, Devices and Systems, 144(5):289-296, October 1997.
Cho W. Moon and Robert K. Brayton. Elimination of dynamic hazards in asynchronous circuits by factoring. In Proc. ACM/IEEE Design Automation Conference, pages 7-13. IEEE Computer Society Press, June 1993.
Cho W. Moon, Paul R. Stephan, and Robert K. Brayton. Specification, synthesis and verification of hazard-free asynchronous circuits. In Proc. International Workshop on Logic Synthesis, May 1991.
Cho W. Moon, Paul R. Stephan, and Robert K. Brayton. Synthesis of hazard-free asynchronous circuits from graphical specifications. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 322-325. IEEE Computer Society Press, November 1991.
Cho W. Moon, Paul R. Stephan, and Robert K. Brayton. Specification, synthesis and verification of hazard-free asynchronous circuits. Journal of VLSI Signal Processing, 7(1/2):85-100, February 1994.
Simon W. Moore and Peter Robinson. Rapid prototyping of self-timed circuits. In Proc. International Conf. Computer Design (ICCD), pages 360-365, October 1998.
S. Moore, P. Robinson, and S. Wilcox. Rotary pipeline processors. IEE Proceedings, Computers and Digital Techniques, 143(5):259-265, September 1996.
S. W. Moore, G. S. Taylor, P. A. Cunningham, R. D. Mullins, and P. Robinson. Interfacing asynchronous and synchronous subsystems. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 129-132, July 2000.
S. W. Moore, G. S. Taylor, P. A. Cunningham, R. D. Mullins, and P. Robinson. Self-calibrating clocks for globally asynchronous locally synchronous systems. In Proc. International Conf. Computer Design (ICCD), September 2000.
Simon Moore, Ross Anderson, Paul Cunningham, Robert Mullins, and George Taylor. Improving smart card security using self-timed circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 211-218, April 2002. (PDF)
Simon Moore, George Taylor, Robert Mullins, and Peter Robinson. Point to point GALS interconnect. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 69-75, April 2002.
Simon Moore, Ross Anderson, Robert Mullins, George Taylor, and Jacques J. A. Fournier. Balanced self-checking asynchronous logic for smart card applications. Microprocessors and Microsystems, 27(9):421-430, October 2003.
Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. An event controlled reconfigurable multi-chip FFT. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 144-153, November 1994.
Shannon V. Morton, Sam S. Appleton, and Michael J. Liebelt. ECSTAC: A fast asynchronous microprocessor. In Asynchronous Design Methodologies, pages 180-189. IEEE Computer Society Press, May 1995.
Antonio Mota, Jose C. Monteiro, and Arlindo L. Oliveira. Power optimization of combinational modules using self-timed precomputation. In Proc. International Symposium on Circuits and Systems, pages 17-20, June 1998.
J. Craig Mudge. An illustration of micropipelines using two-dimensional fourier transform architectures. In G. Musgrave and U. Lauther, editors, Proceedings of VLSI 89, pages 359-368. Elsevier Science Publishers, 1989.
Yuzo Mukai and Yoshihiro Tohma. A method for the realization of fail-safe asynchronous sequential circuits. IEEE Transactions on Computers, 23(7):736-739, July 1974.
O. A. Mukhanov, S. V. Rylov, D. V. Gaidarenko, N. B. Dubash, and V. V. Borzenets. Josephson output interfaces for RSFQ circuits. IEEE Transactions on Applied Superconductivity, 7(2):2826-2831, June 1997.
David E. Muller and W. S. Bartky. A theory of asynchronous circuits. In Proceedings of an International Symposium on the Theory of Switching, pages 204-243. Harvard University Press, April 1959.
J. M. Muller, A. Tisserand, and J. M. Vincent. Asynchronous sub-logarithmic adders. In 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, volume 2, pages 515-518, 1997.
David E. Muller. Asynchronous logics and application to information processing. In Symposium on the Application of Switching Theory to Space Technology, pages 289-297. Stanford University Press, 1962.
D. E. Muller. The general synthesis problem for asynchronous digital networks. In Annual Symposium on Switching and Automata Theory, New York, 1967.
Justin Mullins. Beat the clock. New Scientist, pages 48-52, 19 October 2002.
Jens Muttersbach, Thomas Villiger, Hubert Kaeslin, Norbert Felber, and Wolfgang Fichtner. Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems. In Proc. 12th International ASIC/SOC Conference, pages 317-321, September 1999.
Jens Muttersbach, Thomas Villiger, and Wolfgang Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 52-59, April 2000.
Jens Muttersbach. Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems. PhD thesis, ETH, Zürich, 2001.
Chris Myers and Hans Jacobson. Efficient exact two-level hazard-free logic minimization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 64-73. IEEE Computer Society Press, March 2001.
Chris Myers and Teresa H.-Y. Meng. Synthesis of timed asynchronous circuits. In Proc. International Conf. Computer Design (ICCD), pages 279-282. IEEE Computer Society Press, October 1992. (PostScript)
Chris J. Myers and Teresa H.-Y. Meng. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, 1(2):106-119, June 1993. (PDF)
Chris J. Myers and Hao Zheng. An asynchronous implementation of the MAXLIST algorithm. In 1997 International Conference on Acoustics, Speech, and Signal Processing, April 1997.
C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis and verification of gate-level timed circuits. Technical Report CSL-TR-94-652, Stanford University, January 1995.
C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Automatic synthesis of gate-level timed circuits with choice. In Advanced Research in VLSI, pages 42-58. IEEE Computer Society Press, 1995.
Chris J. Myers, Peter A. Beerel, and Teresa H.-Y. Meng. Technology mapping of timed circuits. In Asynchronous Design Methodologies, IFIP Transactions, pages 138-147. Elsevier Science Publishers, May 1995. (PostScript)
C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.
Chris J. Myers, Wendy Belluomini, Kip Killpack, Eric Mercer, Eric Peskin, and Hao Zheng. Timed circuits: A new paradigm for high-speed design. In Proc. of Asia and South Pacific Design Automation Conference, pages 335-340, February 2001.
Chris J. Myers. Computer-Aided Synthesis and Verification of Gate-Level Timed Circuits. PhD thesis, Dept. of Elec. Eng., Stanford University, October 1995.
Chris Myers. Asynchronous Circuit Design. John Wiley & Sons, 2001.
Radhakrishna Nagalla and Graham Hellestrand. Signal transition graph constraints for synthesis of hazard-free asynchronous circuits with unbounded-gate delays. Formal Methods in System Design, 5(3):245-273, December 1994.
Radhakrishna Nagalla and Graham Hellestrand. Elimination of dynamic hazards from signal transition graphs. In Proc. International Conference on VLSI Design. IEEE Computer Society Press, January 1996.
Radhakrishna Nagalla and Graham Hellestrand. A visual approach for asynchronous circuit synthesis. In Proc. International Conference on VLSI Design, pages 329-335. IEEE Computer Society Press, January 1997.
Y. Nagata and M. Mukaidono. Design of an asynchronous digital system with B-ternary logic. In Proc. IEEE International Symposium on Multiple-Valued Logic, pages 265-271. IEEE Computer Society Press, 1997.
Yasunori Nagata, D. Michael Miller, and Masao Mukaidono. B-ternary logic based asynchronous micropipeline. In Proceedings of the Twenty Ninth IEEE International Symposium on Multi-Valued Logic, pages 402-407, 1998.
J-L. Nagel and C. Piguet. Low-power design of asynchronous microprocessors. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 419-428, October 1998.
Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, and Norbert Imlig. Self-reorganising systems on VLSI circuits. In Proc. International Symposium on Circuits and Systems, volume 4, pages 310-313, 2001.
K. Nanda, S. K. Desai, and S. K. Roy. A new methodology for the design of asynchronous digital circuits. In Proc. International Conference on VLSI Design, pages 342-347. IEEE Computer Society Press, January 1997.
Takashi Nanya and Yoshio Kameda. Pulse-driven delay-insensitive circuits using single-flux-quantum devices. In Proc. International Conf. Computer Design (ICCD), October 1996.
T. Nanya and M. Kuwako. On signal transition causality for self-timed implementation of boolean functions. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
Takashi Nanya and Yoshihiro Tohma. On universal single transition time asynchronous state assignments. IEEE Transactions on Computers, 27(8):781-782, August 1978.
Takashi Nanya and Yoshihiro Tohma. Universal multicode STT state assignments for asynchronous sequential machines. IEEE Transactions on Computers, 28(11):811-818, November 1979.
Takashi Nanya and Yoshihiro Tohma. Design of self-checking asynchronous sequential circuits. In International Symposium on Fault-Tolerant Computing (FTCS), pages 278-280, October 1980.
Takashi Nanya, Yoichiro Ueno, Hiroto Kagotani, Masashi Kuwako, and Akihiro Takamura. TITAC: Design of a quasi-delay-insensitive microprocessor. IEEE Design & Test of Computers, 11(2):50-63, 1994.
T. Nanya, A. Takamura, M. Kuwako, M. Imai, T. Fujii, M. Ozawa, I. Fukasaku, Y. Ueno, F. Okamoto, H. Fujimoto, O. Fujita, M. Yamashina, and M. Fukuma. TITAC-2: A 32-bit scalable-delay-insensitive microprocessor. In Symposium Record of HOT Chips IX, pages 19-32, August 1997.
T. Nanya, A. Takamura, M. Kuwako, M. Imai, M. Ozawa, M. Ozcan, R. Morizawa, and H. Nakamura. Scalable-delay-insensitive design: A high-performance approach to dependable asynchronous systems. In Proc. International Symp. on Future of Intellectual Integrated Electronics, pages 531-540, Sendai, Japan, March 1999. (PDF)
Takashi Nanya. Challenges to dependable asynchronous processor design. In Tsutomu Sasao, editor, Logic Synthesis and Optimization, chapter 9, pages 191-213. Kluwer Academic Publishers, 1993.
Takashi Nanya. A new perspective on asynchronous VLSI system design. In Asia-Pacific Conference on Hardware Description Languages (APCHDL), pages 120-127, January 1996.
R. Negulescu and J. A. Brzozowski. Relative liveness: From intuition to automated verification. In Asynchronous Design Methodologies, pages 108-117. IEEE Computer Society Press, May 1995. (PostScript)
R. Negulescu and J. A. Brzozowski. Relative liveness: From intuition to automated verification. Formal Methods in System Design, 12(1):73-115, January 1998.
Radu Negulescu and Xiaohua Kong. Semi-hiding operators and the analysis of active-edge specifications for digital circuits. In In Proceedings of the International Conference on Application of Concurrency to System Design (ICACSD),, 2001. (PDF)
Radu Negulescu and Ad Peeters. Verification of speed-dependences in single-rail handshake circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 159-170, 1998.
Radu Negulescu. Process spaces. Technical Report CS-95-48, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, December 1995.
Radu Negulescu. A technique for finding and verifying speed-dependences in gate circuits. In Proc. International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), Austin, Texas, USA, December 1997.
Radu Negulescu. A technique for finding and verifying speed-dependences in gate circuits. Research Report CS-97-28, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, August 1997.
R. Negulescu. Event-driven verification of switch-level correctness concerns. In Int. Conf. on Application of Concurrency to System Design, March 1998.
Radu Negulescu. Process Spaces and Formal Verification of Asynchronous Circuits. PhD thesis, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, August 1998. (PostScript)
Radu Negulescu. General testers for asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 28-38. IEEE Computer Society Press, April 2004.
C. L. Nehaniv. Self-reproduction in asynchronous cellular automata. In Proceedings of the NASA/DoD Conference on Evolvable Hardware, pages 201-209, 2002.
M arm Neidengard and Bradley A. Minch. Hysteretic threshold logic and quasi-delay insensitive asynchronous design. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 49(10):1423-1428, October 2002.
Loc Bao Nguen, M. Perkowski, and L. Jozwiak. Design of self-synchronized component FSMs for self-timed systems. In Proceedings 24th EUROMICRO Conference, pages 253-260, 1998.
Christian D. Nielsen and Michael Kishinevsky. Performance analysis based on timing simulation. In Proc. ACM/IEEE Design Automation Conference, pages 70-76, June 1994.
Christian D. Nielsen and Alain J. Martin. Design of a delay-insensitive multiply-accumulate unit. In Proc. Hawaii International Conf. System Sciences, volume I, pages 379-388. IEEE Computer Society Press, January 1993.
Christian D. Nielsen and Alain J. Martin. Design of a delay-insensitive multiply-accumulate unit. Integration, the VLSI journal, 15(3):291-311, October 1993.
Lars Skovby Nielsen and Jens Sparsø. Low-power operation using self-timed and adaptive scaling of the supply voltage. In 1994 International Workshop on Low Power, Napa, California, April 1994.
L. S. Nielsen and J. Sparsø. A low-power asynchronous data-path for a FIR filter bank. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
L. S. Nielsen and J. Sparsø. An 85 muW asynchronous filter-bank for a digital hearing aid. In International Solid State Circuits Conference, February 1998.
Lars S. Nielsen and Jens Sparsø. Designing asynchronous circuits for low-power: An IFIR filter bank for a digital hearing aid. Proceedings of the IEEE, 87(2):268-281, February 1999.
L. S. Nielsen and J. Staunstrup. Design and verification of a self-timed RAM. In Proceedings of the IFIP International Conference on VLSI, 1995.
C. D. Nielsen, J. Staunstrup, and S. R. Jones. Potential performance advantages of delay insensitivity. In Proceedings of Workshop on Silicon Architectures for Neural Nets, St. Paul-de-Vence, France, November 1990. (PostScript)
Christian Dalsgaard Nielsen, Jørgen Staunstrup, and Simon Jones. A delay-insensitive neural network engine. In Will R. Moore, editor, Proceedings of the Workshop on VLSI for Neural Networks, pages 367-376, September 1991.
L. S. Nielsen, C. Niessen, J. Sparsø, and C. H. van Berkel. Low-power operation using self-timed and adaptive scaling of the supply voltage. IEEE Transactions on VLSI Systems, 2(4):391-397, December 1994.
Christian D. Nielsen. Evaluation of function blocks designs. Technical Report ID-TR: 1994-135, Dept. of Computer Science, Technical University of Denmark, Lyngby, 1994.
Christian D. Nielsen. Evaluation of function blocks for asynchronous design. In Proc. European Design Automation Conference (EURO-DAC), pages 454-459. IEEE Computer Society Press, September 1994.
Christian D. Nielsen. Performance Aspects of Delay-Insensitive Design. PhD thesis, Dept. of Computer Science, Technical University of Denmark, Lyngby, 1994.
Lars Skovby Nielsen. Low-power Asynchronous VLSI Design. PhD thesis, Department of Information Technology, Technical University of Denmark, 1997.
Cees Niessen, C. H. (Kees) van Berkel, Martin Rem, and Ronald W. J. J. Saeijs. VLSI programming and silicon compilation: A novel approach from Philips Research. In Proc. International Conf. Computer Design (ICCD), pages 150-151, Rye Brook, New York, 1988. IEEE Computer Society Press.
Th. Nirschl, B. Wicht, and D. Schmitt-Landsiedel. High speed, low power design rules for SRAM precharge and self-timing under technology variations. In Power and Timing Modeling, Optimization and Simulation (PATMOS), 2001.
Bernhard J. Nordmann. Modular asynchronous control design. IEEE Transactions on Computers, 26(3):196-207, March 1977.
R. Nouta, M. Sim, and Gunawan. Two self-timed handshake controllers for high speed applications. In Proc. International Symposium on Circuits and Systems, volume 5, pages 2124-2127, 1992.
S. M. Nowick and B. Coates. Automated design of high-performance asynchronous state machines. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
Steven M. Nowick and David L. Dill. Practicality of state-machine verification of speed-independent circuits. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 266-269. IEEE Computer Society Press, November 1989.
Steven M. Nowick and David L. Dill. Automatic synthesis of locally-clocked asynchronous state machines. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 318-321. IEEE Computer Society Press, November 1991. (PostScript)
Steven M. Nowick and David L. Dill. Synthesis of asynchronous state machines using a local clock. In Proc. International Conf. Computer Design (ICCD), pages 192-197. IEEE Computer Society Press, October 1991. (PostScript)
Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. In Proc. International Conf. Computer-Aided Design (ICCAD). IEEE Computer Society Press, November 1992. (PostScript)
Steven M. Nowick and David L. Dill. Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Transactions on Computer-Aided Design, 14(8):986-997, August 1995.
Steven M. Nowick and Charles W. O 'Donnell. On the existence of hazard-free multi-level logic. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 109-120. IEEE Computer Society Press, May 2003.
S. M. Nowick and M. Theobald. Synthesis of low-power asynchronous circuits in a specified environment. In International Symposium on Low Power Electronics and Design, pages 92-95, 1997.
Steven M. Nowick, Kenneth Y. Yun, and David L. Dill. Practical asynchronous controller design. In Proc. International Conf. Computer Design (ICCD), pages 341-345. IEEE Computer Society Press, October 1992. (PostScript) (PDF)
Steven M. Nowick, Mark E. Dean, David L. Dill, and Mark Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. In Proc. Hawaii International Conf. System Sciences, volume I, pages 419-427. IEEE Computer Society Press, January 1993.
Steven M. Nowick, Mark E. Dean, David L. Dill, and Mark Horowitz. The design of a high-performance cache controller: a case study in asynchronous synthesis. Integration, the VLSI journal, 15(3):241-262, October 1993.
S. Nowick, N. Jha, and F.-C. Cheng. Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. In Proc. International Conference on VLSI Design, January 1995.
S. M. Nowick, N. K. Jha, and F.-C. Cheng. Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability. IEEE Transactions on Computer-Aided Design, 16(12):1514-1521, December 1997.
Steven M. Nowick, Kenneth Y. Yun, and Peter A. Beerel. Speculative completion for the design of high-performance asynchronous dynamic adders. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 210-223. IEEE Computer Society Press, April 1997. (PostScript) (PDF)
Steven M. Nowick, Mark B. Josephs, and C. H. (Kees) van Berkel. Scanning the special issue on asynchronous circuits and systems. Proceedings of the IEEE, 87(2):219-222, February 1999.
Steven M. Nowick. Automatic Synthesis of Burst-Mode Asynchronous Controllers. PhD thesis, Stanford University, Department of Computer Science, 1993.
S. M. Nowick. Design of a low-latency asynchronous adder using speculative completion. IEE Proceedings, Computers and Digital Techniques, 143(5):301-307, September 1996.
Jari Nurmi, Pekka Seppa, Tommi Raita-aho, and Mika Hoffren. A high-speed self-timed FIR processor implementation. Technical report, Tampere University of Technology, Finland, 1999. (PostScript)
Mika Nyström and Alain Martin. Asynchronous Pulse Logic. Kluwer Academic Publishers, 2002.
Mika Nyström, Elaine Ou, and Alain Martin. An 8-bit digital divider implemented in asynchronous pulse logic. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 229-239. IEEE Computer Society Press, April 2004.
Mika Nyström. Asynchronous Pulse Logic. PhD thesis, California Institute of Technology, May 2001. Caltech Computer Science Technical Report 2001.011.
J. Oldfield and C. Kappler. Implementing self-timed systems: comparison of configurable arrays with full custom circuits. In FPGAs: International Workshop on Programmable Logic and Applications. Abingdon EE&CS Books, 1991.
John O'Leary and Geoffrey Brown. Synchronous emulation of asynchronous circuits. IEEE Transactions on Computer-Aided Design, 16(2):205-209, February 1997.
John O'Leary. A model and proof technique for verifying hardware compilers for communicating processes. PhD thesis, Cornell University, 1995.
Mauro Olivieri and Alessandro De Gloria. Hardware design of asynchronous fuzzy controllers. IEEE Trans. on Fuzzy Systems, 4(3), August 1996.
M. Olivieri. Translating occam constructs into delay-insensitive circuits: a trace theory-based proof. Technical Report CPSI92-1, Dept. of Biophys. and Electronic Eng., Univ. of Genoa, Italy, 1992.
M. Olivieri. Design of synchronous and asynchronous variable-latency pipelined multipliers. IEEE Transactions on VLSI Systems, 9(2), May 2001.
T. Ono-Tesfaye, C. Kern, and M. R. Greenstreet. Verifying a self-timed divider. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 146-158, 1998.
Fredrik Orava. Verifying safety and deadlock properties of networks of asynchronously communicating processes. In Ed Brinksma, Guiseppe Scollo, and Chris A. Vissers, editors, Protocol Specification, Testing and Verification: Proceedings of the 9th International IFIP WG 6.1 Workshop, 1989.
Severo M. Ornstein, Mishell J. Stucki, and Wesley A. Clark. A functional description of macromodules. In AFIPS Conference Proceedings: 1967 Spring Joint Computer Conference, volume 30, pages 337-355, Atlantic City, NJ, 1967. Academic Press.
G. Orton, L. E. Peppard, and S. E. Tavares. A fast asynchronous RSA encryption chip. In Proc. IEEE Custom Integrated Circuits Conference, pages 439-442. IEEE Computer Society Press, May 1986.
Motokazu Ozawa, Masashi Imai, Yoichiro Ueno, Hiroshi Nakamura, and Takashi Nanya. Performance evaluation of cascade ALU architecture for asynchronous super-scalar processors. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 162-172. IEEE Computer Society Press, March 2001.
Metehan Özcan, Masashi Imai, and Takashi Nanya. Generation and verification of timing constraints for fine-grain pipelined asynchronous data-path circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 109-114, April 2002. (PDF)
Recep O. Ozdag and Peter A. Beerel. High-speed QDI asynchronous pipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 13-22, April 2002.
R. Ozdag and P. Beerel. A channel based asynchronous low power high performance standard-cell based sequential decoder implemented with QDI templates. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 187-197. IEEE Computer Society Press, April 2004.
Recep O. Ozdag, Montek Singh, Peter A. Beerel, and Steven M. Nowick. High-speed non-linear asynchronous pipelines. In Proc. Design, Automation and Test in Europe (DATE), pages 1000-10007, March 2002.
Hakan Özdemir, Asim Kepkep, Banu Pamir, Yusuf Leblebici, and Ugur Çilingiroglu. A capacitive threshold-logic gate. IEEE Journal of Solid-State Circuits, 31(8):1141-1150, August 1996.
Fusin Ozguner. Design of totally self-checking asynchronous and synchronous sequential machines. In International Symposium on Fault-Tolerant Computing (FTCS), pages 124-129, June 1977.
L. E. M. Brackenbury P. A. Riocreux, M. J. G. Lewis. Power reduction in self-timed circuits using early-open latch controllers. Electronics Letters, 36(2):115-116, 2000.
S. Pagey, G. Venkatesh, and S. Sherlekar. Issues in fault modeling and testing of micropipelines. In Proc. of the Asian Test Symposium, Hiroshima, Japan, November 1992.
Sandeep Pagey, Ajay Khoche, and Erik Brunvand. DFT for fast testing of self-timed control circuits. In Proc. of the Asian Test Symposium, pages 382-386, 1995.
Sandeep Pagey. Fast functional testing of delay-insensitive circuits. In Proc. of the Asian Test Symposium, pages 375-381, 1995.
G. S. Panagiotaras and O. G. Koufopavlou. Area-reduction in asynchronous circuits by signal transition graph transformations. In Power and Timing Modeling, Optimization and Simulation (PATMOS), September 1997.
Y. W. Pang and C. S. Choy. An asynchronous matrix multiplier. In IEEE Region 10 International Conference on Microelectronics and VLSI. `Asia-Pacific Microelectronics 2000', pages 315-318, November 1995.
Peggy Pang and Mark Greenstreet. Self-timed meshes are faster than synchronous. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 30-39. IEEE Computer Society Press, April 1997.
Tin-Chak Johnson Pang, Chiu-Sing Oliver Choy, Cheong-Fat Chan, and Wai-Kuen Cham. A self-timed ICT chip for image coding. IEEE Transactions on Circuits and Systems for Video Technology, 9(6):856-860, 1999.
Chansub Park and Duckjin Chung. Modified asynchronous wave-pipelining. Electronics Letters, 36(4):295-297, 2000.
Sung Bum Park and Takashi Nanya. A direct verification of CSC property of STG/FCs for asynchronous circuit design. In Asia-Pacific Conference on Hardware Description Languages (APCHDL), pages 169-176, October 1994.
Sung Bum Park and Takashi Nanya. Automatic synthesis of speed-independent circuits from signal transition graph specifications. In Proc. International Conference on VLSI Design, pages 389-392, January 1996.
Sung Bum Park and T. Nanya. Synthesis of asynchronous circuits from signal transition graph specifications. IEICE Transactions on Information and Systems, E80-D(3):326-335, March 1997.
J. Pasanen and B. Oelmann. Locally clocked AFSMs with dynamic latch implementation. In IEEE International Conference on Electronics, Circuits and Systems, pages 1643-1646, 1999.
Enric Pastor and Jordi Cortadella. P-time unique state coding algorithms for signal transition graphs. Technical report, Universitat Politècnica de Catalunya, 1993. (PostScript)
Enric Pastor and Jordi Cortadella. Polynomial algorithms for the synthesis of hazard-free circuits from signal transition graphs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 250-254. IEEE Computer Society Press, November 1993. (PostScript)
Enric Pastor, Jordi Cortadella, and Oriol Roig. A new look at the conditions for the synthesis of speed-independent circuits. Technical report, Universitat Politècnica de Catalunya, 1994. (PostScript)
Enric Pastor, Oriol Roig, Jordi Cortadella, and Rosa M. Badia. Petri net analysis using boolean manipulation. In 15th International Conference on Application and Theory of Petri Nets, June 1994. (PostScript)
E. Pastor, J. Cortadella, O. Roig, and A. Kondratyev. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference, pages 340-347. IEEE Computer Society Press, March 1996.
Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. IEEE Transactions on Computer-Aided Design, 17(11):1108-1129, November 1998.
Enric Pastor. Structural Methods for the Synthesis of Asynchronous Circuits from Signal Transition Graphs. PhD thesis, Univsitat Politècnia de Catalunya, February 1996.
V. Patel and K. Steptoe. Evaluation of self-timed systems for VLSI. Electronics Letters, 25(3):215-217, February 1989.
Priyadarsan Patra and Donald Fussel. Efficient building blocks for delay insensitive circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 196-205, November 1994.
Priyadarsan Patra and Donald S. Fussell. Building-blocks for designing DI circuits. Technical report tr93-23, Dept. of Computer Sciences, The Univ of Texas at Austin, November 1993.
Priyadarsan Patra and Donald S. Fussell. Optimization of delay-insensitive circuits -- a case study. Technical report, Dept. of Computer Sciences, The Univ of Texas at Austin, July 1994. Technical Report.
Priyadarsan Patra and Donald S. Fussell. Fully asynchronous, robust, high-throughput arithmetic structures. In Proc. of Eighth International Conference on VLSI Design. IEEE Computer Society Press, January 1995.
Priyadarsan Patra and Donald S. Fussell. Power-efficient delay-insensitive codes for data transmission. In Proc. Hawaii International Conf. System Sciences, January 1995.
Priyadarsan Patra and Donald S. Fussell. Conservative delay-insensitive circuits. In Workshop on Physics and Computation, pages 248-259, November 1996.
Priyadarsan Patra and Donald S. Fussell. Efficient delay-insensitive RSFQ circuits. In Proc. International Conf. Computer Design (ICCD), October 1996.
Priyadarsan Patra, Donald S. Fussell, and Stanislav Polonsky. Delay insensitive logic for RSFQ superconductor technology. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 42-53. IEEE Computer Society Press, April 1997.
Priyadarsan Patra. From parallel programs to asynchronous VLSI. Technical report, Dept. of Computer Sciences, The Univ of Texas at Austin, 1991. Appears in report collection CS-TR-91-18.
Priyadarsan Patra. Approaches to Design of Circuits for Low-Power Computation. PhD thesis, The University of Texas at Austin, 1995.
N. C. Paver, P. Day, S. B. Furber, J. D. Garside, and J. V. Woods. Register locking in an asynchronous microprocessor. In Proc. International Conf. Computer Design (ICCD), pages 351-355. IEEE Computer Society Press, October 1992. (PostScript)
N. C. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, and J. Liu. A low-power, low-noise configurable self-timed DSP. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 32-42, 1998.
N. C. Paver. The Design and Implementation of an Asynchronous Microprocessor. PhD thesis, Department of Computer Science, University of Manchester, June 1994. (PostScript)
R. E. Payne. Self-timed FPGA systems. In W. Moore and W. Luk, editors, Fifth International workshop on Field Programmable Logic and Applications, volume 975 of Lecture Notes in Computer Science, pages 21-35, 1995.
R. Payne. Asynchronous FPGA architectures. IEE Proceedings, Computers and Digital Techniques, 143(5):282-286, September 1996.
R. C. Pearce, J. A. Field, and W. D. Little. Asynchronous arbiter module. IEEE Transactions on Computers, 24:931-932, September 1975.
Ad Peeters. The `Asynchronous' Bibliography Homepage. http://www.win.tue.nl/async-bib/async.html.
Ad Peeters. The `Asynchronous' Bibliography ( sc Bib TeX ) database file async.bib. http://www.win.tue.nl/async-bib/doc/async.bib. Corresponding e-mail address: async-bib@win.tue.nl. (PostScript) (PDF)
Ad Peeters and Kees van Berkel. Single-rail handshake circuits. In Asynchronous Design Methodologies, pages 53-62. IEEE Computer Society Press, May 1995.
Ad Peeters and Kees van Berkel. Synchronous handshake circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 86-95. IEEE Computer Society Press, March 2001.
Ad Peeters. Decomposition of delay-insensitive circuits. Computing Science Notes 90/04, Dept. of Math. and C.S., Eindhoven Univ. of Technology, April 1990.
Ad M. G. Peeters. Single-Rail Handshake Circuits. PhD thesis, Eindhoven University of Technology, June 1996. (PostScript) (PDF)
Ad Peeters. Support for interface design in Tangram. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 57-64, July 2000.
M. A. Peña and J. Cortadella. Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
Marco A. Peña, Jordi Cortadella, Alex Kondratyev, and Enric Pastor. Formal verification of safety properties in timed circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2-11. IEEE Computer Society Press, April 2000.
Paul Pénzes and Alain J. Martin. Energy-delay efficiency of vlsi computations. In Proc. of the Great Lakes Symposium on VLSI, 2002. (PostScript)
Paul I. Pénzes and Alain J. Martin. An energy estimation method for asynchronous circuits with application to an asynchronous microprocessor. In Proc. Design, Automation and Test in Europe (DATE), pages 640-647, March 2002.
Paul Pénzes, Mika Nyström, and Alain J. Martin. Transistor sizing of energy-delay-efficient circuits. In Proc. of the Great Lakes Symposium on VLSI, 2002. (PostScript)
Paul Pénzes. Energy-delay Complexity of Asynchronous Circuits. PhD thesis, California Institute of Technology, 2002. (PostScript)
F. Peper, T. Isokawa, N. Kouda, and N. Matsui. Self-timed cellular automata and their computational ability. Future Generation Computer Systems, 18:893-904, 2002.
Ferdinand Peper, Jia Lee, Susumu Adachi, and Shinro Mashiko. Laying out circuits on asynchronous cellular arrays: a step towards feasible nanocomputers? Nanotechnology, 14:469-485, 2003.
F. Peper. Spatial computing on self-timed cellular automata. In Proc. 2nd Conf. on Unconventional Models of Computation (UCM2K), pages 202-214. Springer-Verlag, 2000.
R. Perez-Ribas and A. Guyot. DCFL- and DPTL-based approaches to self-timed GaAs circuits. In Proc. European Solid-State Circuits Conference (ESSCIRC), pages 186-189, September 1995.
R. Perez-Ribas and A. Guyot. Can asynchronous design reduce power dissipation in GaAs ICs. In Power and Timing Modeling, Optimization and Simulation (PATMOS), September 1996.
R. Perez-Ribas, A. Bernal, and A. Guyot. A low-power differential cross-coupled FET logic for GaAs asynchronous design. In 4th European Galium Arsenide and Related III-V Compounds Application Symposium (GAAS'96), pages 1-4, June 1996.
R. Perez-Ribas, R. Kanan, and A. Guyot. Differential-type structures and C-elements for GaAs MESFET asynchronous circuits. In 11th Congress of the Brazilian Microelectronic Society (XI Submicro), August 1996.
S. Perri, P. Corsonello, and G. Cocorullo. Designing high speed asynchronous pipelines. In Proceedings of the 26th Euromicro Conference, pages 394-399, 2000.
Eric Robert Peskin. Protocol Selection, Implementation, and Analysis for Asynchronous Circuits. Ph.D. dissertation, The University of Utah, August 2002. (PostScript) (PDF)
Francesco Pessolano and Mark B. Josephs. A low-power, high-speed stack controller designed using asynchronous circuit techniques. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 387-396, October 1998.
Francesco Pessolano and Joep Kessels. Asynchronous first-in first-out queues. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 1918 of Lecture Notes in Computer Science, pages 178-186, September 2000.
F. Pessolano, R. Mariani, and R. Saletti. An innovative multiple-valued asynchronous system design technique. In Power and Timing Modeling, Optimization and Simulation (PATMOS), September 1997.
Francesco Pessolano, Martin E. Bush, and Dave Protheroe. The design of the Gravity asynchronous processor core. In 14th European Conference on Circuit Theory and Design (ECCTD), 1999.
Francesco Pessolano, Dave Protheroe, and Martin E. Bush. Data-dependent clocked logic. In 14th European Conference on Circuit Theory and Design (ECCTD), 1999.
Francesco Pessolano, Joep Kessels, and Ad Peeters. MDSP: a high-performance low-power DSP architecture. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 2451 of Lecture Notes in Computer Science, September 2002.
Francesco Pessolano. A flexible delay-insensitive computer architecture. In 7th NASA Symposium on VLSI design, 1998.
F. Pessolano. An enhanced locking register file for asynchronous processors. In First Conference on Electronics and Photonics (PREP99), 1999.
F. Pessolano. Heterogeneous clustered processors: Organisation and design. In EuroPar'99 - Parallel Processing, volume 1685 of Lecture Notes in Computer Science, 1999.
F. Pessolano. IAESiD: Internally asynchronous externally synchronous in-chip design. In First Conference on Electronics and Photonics (PREP99), 1999.
F. Pessolano. Introducing delay probability graphs with the design of a 32-bit asynchronous alu. In 2nd Intl. Conference on Electronics Circuits and Systems, 1999.
O. A. Petlin and S. B. Furber. Designing C-elements for testability. Technical Report UMCS-95-10-2, Department of Computer Science, University of Manchester, 1995. (PostScript)
O. A. Petlin and S. B. Furber. Scan testing of asynchronous sequential circuits. In Proc. of the Great Lakes Symposium on VLSI, pages 224-229, March 1995. (PostScript)
O. A. Petlin and S. B. Furber. Scan testing of micropipelines. In Proc. IEEE VLSI Test Symposium, pages 296-301, May 1995. (PostScript)
O. A. Petlin and S. B. Furber. Built-in self-testing of micropipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 22-29. IEEE Computer Society Press, April 1997. (PostScript)
O. A. Petlin, S. B. Furber, A. M. Romankevich, and V. V. Groll. Designing asynchronous sequential circuits for random pattern testability. IEE Proceedings, Computers and Digital Techniques, 142(4), 1995. (PostScript)
O. A. Petlin. Random testing of asynchronous VLSI circuits. Master's thesis, Department of Computer Science, University of Manchester, 1994. (PostScript)
Miroslav Pechoucek. Anomalous response times of input synchronizers. IEEE Transactions on Computers, 25(2):133-139, February 1976.
Stanislaw J. Piestrak and Takashi Nanya. Towards totally self-checking quasi-delay-insensitive systems. In International Symposium on Fault-Tolerant Computing (FTCS), pages 228-237, June 1995.
S. J. Piestrak. Design of totally self-checking code disjoint inverter-free PLA for separable unordered codes. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
S. J. Piestrak. Membership test logic for delay-insensitive codes. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 194-204, 1998.
C. Piguet and V. von Kaenel. Logic synthesis of a PLL phase frequency detector. IEE Proceedings, Computers and Digital Techniques, 144(6):381-385, November 1997.
C. Piguet and J. Zahnd. Design of speed-independent CMOS cells from signal transition graphs. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 357-366, October 1998.
C. Piguet and J. Zahnd. Signal-transition graphs-based design of speed-independent CMOS circuits. In Proc. European Solid-State Circuits Conference (ESSCIRC), pages 432-435, September 1998.
C. Piguet and J. Zahnd. STG-based synthesis of speed-independent CMOS cells. In Workshop on Exploitation of STG-Based Design Technology, July 1998.
Christian Piguet. Logic synthesis of asynchronous circuits. In Proc. IEEE Custom Integrated Circuits Conference, pages 26.6.1-62.6.4, 1990.
Christian Piguet. Logic synthesis of race-free asynchronous CMOS circuits. IEEE Journal of Solid-State Circuits, 26(3):371-380, March 1991.
C. Piguet. Low-power and low-voltage CMOS digital design. In Microelectronic-Engineering; Low-Power, Low-Voltage Integrated Circuits: Technology and Design, volume 39, pages 179-208, June 1997.
C. Piguet. Synthesis of asynchronous CMOS circuits with negative gates. Journal of Solid State Devices and Circuits (Brazil), 5(2):12-20, July 1997.
C. Piguet. Design of low-power libraries. In IEEE International Conference on Electronics, Circuits and Systems, pages 175-180, 1998.
C. Piguet. Supplementary condition for STG-designed speed-independent circuits. Electronics Letters, 34(7):620-622, 1998.
C. Piguet. Robustness of asynchronous sequential standard cells in a synchronous environment. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 103-120, July 2000.
L. Plana and S. Nowick. Concurrency-oriented optimization for low-power asynchronous systems. In International Symposium on Low Power Electronics and Design, pages 151-156, August 1996.
Luis A. Plana and Steven M. Nowick. Architectural optimization for low-power nonpipelined asynchronous systems. IEEE Transactions on VLSI Systems, 6(1):56-65, March 1998.
Luis A. Plana and Stephen H. Unger. Pulse-mode macromodular systems. In Proc. International Conf. Computer Design (ICCD), pages 348-353, October 1998.
L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, J. D. Garside, and S. Temple. SPA - a synthesisable amulet core for smartcard applications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 201-210, April 2002. (PDF)
L. A. Plana, P. A. Riocreux, W. J. Bainbridge, A. Bardsley, S. Temple, J. D. Garside, and Z. C. Yu. SPA--- a secure Amulet core for smartcard applications. Microprocessors and Microsystems, 27(9):431-446, October 2003.
Luis Angel Plana. Contributions to the Design of Asynchronous Macromodular Systems. PhD thesis, Department of Computer Science, Columbia University, 1998. Technical report CUCS-001-99. (PostScript)
J. Plosila and K. Sere. Action systems in pipelined processor design. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 156-166. IEEE Computer Society Press, April 1997.
J. Plosila, R. Ruksenas, and K. Sere. Delay-insensitive circuits and action systems. Technical Report TR60, Turku Centre for Computer Science, November 1996.
J. Plosila, R. Ruksenas, and K. Sere. Handshaking expansion as action system refinement. Technical Report TR55, Turku Centre for Computer Science, October 1996.
J. Plosila, R. Ruksenas, and K. Sere. Action systems synthesis of di circuits. Technical Report TR149, Turku Centre for Computer Science, December 1997.
Juha Plosila, Tiberiu Seceleanu, and Pasi Liljeberg. Implementation of a self-timed segmented bus. IEEE Design & Test of Computers, 20(6):44-50, 2003.
W. W. Plummer. Asynchronous arbiters. IEEE Transactions on Computers, 21(1):37-42, January 1972.
S. Polonsky. RSFQ: What we know and what we don't. In Proc. International Conf. Computer Design (ICCD), October 1996.
N. R. Poole. Self-timed logic circuits. Electronics and Communication Engineering Journal, 6(6):261-270, 1994.
N. R. Poole. Auxiliary functions for completion detection in self-timed systems. Electronics Letters, 31(21):1805-1806, October 1995.
Clemenz L. Portmann and Teresa H. Y. Meng. Metastability in CMOS library elements in reduced supply and technology scaled applications. IEEE Journal of Solid-State Circuits, 30(1):39-46, January 1995.
J. Povazanec, C.S. Choy, and C.F. Chan. Asynchronous logic in it-bit-serial arithmetic. In IEEE International Conference on Electronics, Circuits and Systems, pages 175-178, September 1998.
G. Privat, F. Robin, M. Renaudin, and B. El Hassan. A fine-grain asynchronous VLSI cellular array processor architecture. In Proc. International Symposium on Circuits and Systems, 1995.
David K. Probst and Hon F. Li. Abstract specification, composition and proof of correctness of delay-insensitive circuits and systems. Technical Report CS-VLSI-88-2, Dept. of C.S., Concordia Univ., Montreal, Canada, April 1988.
David K. Probst and Hon F. Li. Partial-order model checking of delay-insensitive systems. In R. Hobson, editor, Proceedings of 1989 Canadian Conference on VLSI, pages 73-80, October 1989.
David K. Probst and Hon F. Li. Using partial-order semantics to avoid the state explosion problem in asynchronous systems. In Robert P. Kurshan and Edmund M. Clarke, editors, Proc. International Workshop on Computer Aided Verification, volume 531 of Lecture Notes in Computer Science, pages 146-155. Springer-Verlag, 1990.
David K. Probst and Hon F. Li. Partial-order model checking: a guide for the perplexed. In K. G. Larsen and A. Skou, editors, Proc. International Workshop on Computer Aided Verification, volume 575 of Lecture Notes in Computer Science, pages 322-331. Springer-Verlag, 1991.
Douglas A. Pucknell. Event-driven logic (EDL) approach to digital system representation and related design processes. IEE Proceedings, Computers and Digital Techniques, 140(2), March 1993.
R. Puri and J. Gu. Signal transition graph constraints for speed-independent circuit synthesis. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1686-1689. IEEE Computer Society Press, 1993.
Ruchir Puri and Jun Gu. Asynchronous circuit synthesis; persistency and complete state coding constraints in signal transition graphs. Int. Journal Electronics, 75(5):933-940, 1993.
Ruchir Puri and Jun Gu. Area efficient synthesis of asynchronous interface circuits. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, October 1994.
Ruchir Puri and Jun Gu. A divide-and-conquer approach for asynchronous interface synthesis. In Proc. International Symposium on High-Level Synthesis, pages 118-125. IEEE Computer Society Press, May 1994.
Ruchir Puri and Jun Gu. A modular partitioning approach for asynchronous circuit synthesis. In Proc. ACM/IEEE Design Automation Conference, pages 63-69, June 1994.
S. Purushothaman and P. A. Subrahmanyam. An algebraic basis for specifying and reasoning about protocols for designing self timed circuits. In F. Anceau and E. J. Aas, editors, VLSI 83: VLSI Design of Digital Systems, pages 133-144. IFIP, Elsevier Science Publishers, August 1983.
Gianfranco R. Putzolu. A heuristic algorithm for the testing of asynchronous circuits. IEEE Transactions on Computers, 20(6):639-647, June 1970.
Ravi Ramachandran and Shih-Lien Lu. Efficient arithmetic using self-timing. IEEE Transactions on VLSI Systems, 4(4):445-454, December 1996.
C. Ramchandani. Analysis of asynchronous concurrent systems by timed Petri nets. Technical Report Project MAC Tech. Rep. 120, Massachusetts Inst. of Tech., February 1974.
Deepak Rana, Steven P. Levitan, David A. Carlson, and Charles E. Hutchinson. A testable asynchronous systolic array implementation of an IIR filter. In Proc. IEEE Custom Integrated Circuits Conference, pages 90-93. IEEE Computer Society Press, May 1986.
V. M. Rao and B. Mowrouzian. Design and implementation of asynchronous parallel multiply-accumulate arithmetic architectures. In Proc. of the Midwest Symposium on Circuits and Systems, pages 761-764, 1996.
V.S.P. Rapaka and D. Marculescu. A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores. In International Symposium on Low Power Electronics and Design, pages 372-377, 2003.
V. E. F. Rebello. On the Distribution of Control in Asynchronous Processor Architectures. PhD thesis, Department of Computer Science, The University of Edinburgh, UK, 1996. (PostScript)
Robert B. Reese and Mitchell A. Thorntonand Cherrice Traver. A coarse-grain phased logic CPU. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 2-13. IEEE Computer Society Press, May 2003.
Robert B. Reese, Mitch A. Thornton, and Cherrice Traver. Arithmetic logic circuits using self-timed bit level dataflow and early evaluation. In Proc. International Conf. Computer Design (ICCD), pages 18-23, November 2001.
I. Reicher and M. Yoeli. Net-based modeling of communicating parallel processes with applications to VLSI Design. Technical Report 532, Dept. Comp. Science, Technion, Haifa, Israel, 1988.
Martin Rem. Concurrent computations and VLSI circuits. In M. Broy, editor, Control Flow and Data Flow: Concepts of Distributed Programming, volume F14 of NATO ASI Series, pages 399-437. Springer-Verlag, 1985.
Martin Rem. Trace theory and systolic computations. In J. W. de Bakker, A. J. Nijman, and P. C. Treleaven, editors, PARLE: Parallel Architectures and Languages Europe, Vol. I, volume 258 of Lecture Notes in Computer Science, pages 14-33. Springer-Verlag, 1987.
Martin Rem. The nature of delay-insensitive computing. In Graham Birtwistle, editor, IV Higher Order Workshop, Banff 1990, pages 105-122. Springer-Verlag, 1991.
Marc Renaudin and Bachar El Hassan. The design of fast asynchronous adder structures and their implementation using DCVS logic. In Proc. International Symposium on Circuits and Systems, volume 4, pages 291-294, 1994.
M. Renaudin and J. B. Rigaud. Modelling and design/synthesis of arbitration problems. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 121-128, July 2000.
Marc Renaudin, Bachar El Hassan, and Alain Guyot. New asynchronous pipeline scheme: Application to the design of a self-timed ring divider. IEEE Journal of Solid-State Circuits, 31(7):1001-1013, July 1996.
M. Renaudin, P. Vivet, and F. Robin. ASPRO-216: A standard-cell QDI 16-bit RISC asynchronous microprocessor. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 22-31, 1998.
M. Renaudin, P. Vivet, and F. Robin. A design framework for asynchronous/synchronous circuits based on CHP to HDL translation. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 135-144, April 1999.
C. A. Rey and J. Vaucher. Self-synchronized asynchronous sequential machines. IEEE Transactions on Computers, 23(12):1306-1311, December 1974.
William F. Richardson and Erik Brunvand. The NSR processor prototype. Technical report, Dept. of Computer Science, University of Utah, August 1994. (PostScript)
W. F. Richardson and E. Brunvand. Precise exception handling for a self-timed processor. In Proc. International Conf. Computer Design (ICCD), pages 32-37. IEEE Computer Society Press, 1995.
W. F. Richardson and E. Brunvand. Architectural considerations for a self-timed decoupled processor. IEE Proceedings, Computers and Digital Techniques, 143(5):251-257, September 1996.
W. F. Richardson and E. Brunvand. An architecture for a self-timed decoupled computer. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
W. F. Richardson. Architectural considerations in a self-timed processor design. PhD thesis, The University of Utah, 1996.
J.-B. Rigaud, J. Quartana, L. Fesquet, and M. Renaudin. High-level modeling and design of asynchronous arbiters for on-chip communication systems. In Proc. Design, Automation and Test in Europe (DATE), page 1090, March 2002.
P. A. Riocreux, L. E. M. Brackenbury, M. Cumpstey, and S. B. Furber. A low-power self-timed Viterbi decoder. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 15-24. IEEE Computer Society Press, March 2001.
F. Robin, M. Renaudin, G. Privat, and N. Van Den Bossche. Functionally asynchronous array processor for morphological filtering of greyscale images. IEE Proceedings, Computers and Digital Techniques, 143(5):273-281, September 1996.
Oriol Roig, Jordi Cortadella, and Enric Pastor. Conservative symbolic model-checking of Petri nets for speed-independent circuit verification. Technical report, Universitat Politècnica de Catalunya, 1994. (PostScript)
Oriol Roig, Jordi Cortadella, and Enric Pastor. Symbolic model checking of Petri nets for the verification of speed-independent circuits. Technical report, Universitat Politècnica de Catalunya, 1994. (PostScript)
Oriol Roig, Jordi Cortadella, and Enric Pastor. Hierarchical gate-level verification of speed-independent circuits. In Asynchronous Design Methodologies, pages 129-137. IEEE Computer Society Press, May 1995. (PostScript)
Oriol Roig, Jordi Cortadella, and Enric Pastor. Verification of asynchronous circuits by BDD-based model checking of Petri nets. In 16th International Conference on the Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, pages 374-391, June 1995. (PostScript)
Oriol Roig, Jordi Cortadella, Marco A. Peña, and Enric Pastor. Automatic generation of synchronous test patterns for asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 620-625, June 1997.
Oriol Roig. Formal Verification and Testing of Asynchronous Circuits. PhD thesis, Univsitat Politècnia de Catalunya, May 1997.
Per Torstein Røine. Asynchronous FIFO buffer for multicomputer applications. Master's thesis, Department of Informatics, University of Oslo, 1994.
Per Torstein Røine. Building fast bundled data circuits with a specialized standard cell library. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 134-143, November 1994.
Per Torstein Røine. A system for asynchronous high-speed chip to chip communication. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
Per Torstein Røine. An asynchronous PRBS error checker for testing high-speed self-clocked serial links. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 133-141, 1998.
Per Torstein Røine. Performance of Synchronous and Asynchronous High-Speed Links: A Practical Experiment. PhD thesis, Faculty of Mathematics and Natural Sciences, University of Oslo, Norway, 2000.
Marly Roncken and Erik Bruls. Test quality of asynchronous circuits: A defect-oriented evaluation. In Proc. International Test Conference, pages 205-214, October 1996.
Marly Roncken and Ronald Saeijs. Linear test times for delay-insensitive circuits: a compilation strategy. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 13-27. Elsevier Science Publishers, 1993.
Marly Roncken, Emile Aarts, and Wim Verhaegh. Optimal scan for pipelined testing: An asynchronous foundation. In Proc. International Test Conference, pages 215-224, October 1996.
Marly Roncken, Ken Stevens, Rajesh Pendurkar, Shai Rotem, and Parimal Pal Chaudhuri. CA-BIST for asynchronous circuits: A case study on the RAPPID asynchronous instruction length decoder. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 62-72. IEEE Computer Society Press, April 2000.
Marly Roncken. Partial scan test for asynchronous circuits illustrated on a DCC error corrector. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 247-256, November 1994.
Marly Roncken. Defect-oriented testability for asynchronous IC's. Proceedings of the IEEE, 87(2):363-375, February 1999.
Fred U. Rosenberger and Charles E. Molnar. Comments on `metastability of CMOS latch/flip-flop'. IEEE Journal of Solid-State Circuits, 27(1):128-130, January 1992. Reply by Robert W. Dutton pages 131-132 of same issue.
Fred U. Rosenberger, Charles E. Molnar, Thomas J. Chaney, and Ting-Pien Fang. Q-modules: Internally clocked delay-insensitive modules. IEEE Transactions on Computers, C-37(9):1005-1018, September 1988.
L. Y. Rosenblum and A. V. Yakovlev. Signal graphs: from self-timed to timed ones. In Proceedings of International Workshop on Timed Petri Nets, pages 199-207, Torino, Italy, July 1985. IEEE Computer Society Press.
R. Rosenmoser, Q. Huang, and F. Piazza. 1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2 mu m CMOS prescalers. In Proc. IEEE Custom Integrated Circuits Conference, pages 387-390, 1994.
Shai Rotem, Ken Stevens, Ran Ginosar, Peter Beerel, Chris Myers, Kenneth Yun, Rakefet Kol, Charles Dike, Marly Roncken, and Boris Agapiev. RAPPID: An asynchronous instruction length decoder. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 60-70, April 1999. (PDF)
G. A. Ruiz and M. A. Manzano. Compact 32-bit CMOS adder in multiple-output DCVS logic for self-timed circuits. IEE Proceedings, Circuits, Devices and Systems, 147(3):183-188, 2000.
G. A. Ruiz and M. A. Manzano. Self-timed multiplier based on canonical signed-digit recoding. IEE Proceedings, Circuits, Devices and Systems, 148(5):235-241, October 2001.
G. A. Ruiz. Compact four bit carry look-ahead CMOS adder in multi-output DCVS logic. Electronics Letters, 32(17):1556-1557, 1996.
G. A. Ruiz. Evaluation of three 32-bit CMOS adders in DCVS logic for self-timed circuits. IEEE Journal of Solid-State Circuits, 33(4):604-613, April 1998.
J. W. J. M. Rutten and M. R. C. M. Berkelaar. Improved state assignments for burst mode finite state machines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 228-239. IEEE Computer Society Press, April 1997.
Jeroen Rutten and Michel Berkelaar. Efficient exact and heuristic minimization of hazard-free logic. In Proc. International Conf. Computer Design (ICCD), pages 152-159, October 1998.
Jeroen Rutten and Michel Berkelaar. Towards muti-level synthesis for asynchronous logic. In Proc. International Workshop on Logic Synthesis, pages 77-82, June 1998.
J. W. J. M. Rutten and M. A. J. Kolsteren. A divide and conquer strategy for hazard free 2-level logic synthesis. In Proc. International Workshop on Logic Synthesis, 1997.
Jeroen Rutten. Asynchronous burst mode finite state machines. In Proc. of the IEEE/ProRISC Symposium on Circuits, Systems and Signal Processing, 1996.
Jeroen Rutten. Synthesis of Asynchronous Burst-Mode Finite State Machines. PhD thesis, Eindhoven University of Technology, April 2000.
N. Saadallah, X. Kong, and R. Negulescu. High speed reduced stack dual lock GasP circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 219-228. IEEE Computer Society Press, April 2004.
Mäart Saarepera and Tomohiro Yoneda. A self-timed implementation of boolean functions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 243-250, April 1999.
M. Sacker, A. Brown, P. Wilson, and A. Rushton. A general purpose behavioural asynchronous synthesis system. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 125-134. IEEE Computer Society Press, April 2004.
Ronald W. J. J. Saeijs and C. H. (Kees) van Berkel. The design of the VLSI image generator ZaP. In Proc. International Conf. Computer Design (ICCD), pages 163-166. IEEE Computer Society Press, 1988.
Mohit Sahni and Takashi Nanya. On the CSC property of signal transition graph specifications for asynchronous circuit design. In Proc. of Asia and South Pacific Design Automation Conference, pages 183-189, February 1998.
A. Saifhashemi and H Pedram. Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. In Proc. ACM/IEEE Design Automation Conference, pages 330-333, June 2003.
H. Saito, A. Kondratyev, J. Cortadella, L. Lavagno, and A. Yakovlev. Bridging modularity and optimality: delay-insensitive interfacing in asynchronous circuits synthesis. In IEEE International Conference on Systems, Man, and Cybernetics, pages 899-904, 1999.
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev. What is the cost of delay insensitivity? In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 169-189, June 1999.
Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, and Alexander Yakovlev. What is the cost of delay insensitivity? In Proc. International Conf. Computer-Aided Design (ICCAD), pages 316-323, November 1999.
H. Saito, A. Kondratyev, and T. Nanya. Design of asynchronous controllers with delay insensitive interface. In Proc. of Asia and South Pacific Design Automation Conference, pages 93-98, 2002.
Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, and Takashi Nanya. Control signal sharing using data-path delay information at control data flow graph descriptions. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 184-193. IEEE Computer Society Press, May 2003.
T. Sakurai. Optimization of CMOS arbiter and synchronizer circuits with submicron MOSFETs. IEEE Journal of Solid-State Circuits, 23(4):901-906, August 1988.
O. Salomon and H. Klar. Self-timed fully pipelined multipliers. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 45-55. Elsevier Science Publishers, 1993.
O. Salomon and H. Klar. Standard cell design for testable self-timed circuits. In Proc. European Solid-State Circuits Conference (ESSCIRC), pages 190-193. Editions Frontières, September 1993.
Fermin Sanchez and Jordi Cortadella. UNRET: A transformation-based technique for software pipelining with resource constraints. Technical report, Universitat Politècnica de Catalunya, 1994. (PostScript)
F. Sanchez and J. Cortadella. Time constrained loop pipelining. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 592-596, November 1995. (PostScript)
Fermin Sanchez and Jordi Cortadella. Register optimization for maximum throughput loop pipelining. Technical report, Universitat Politècnica de Catalunya, 1995. (PostScript)
Mark Santoro and Mark A. Horowitz. SPIM: A pipelined 64x64-bit iterative multiplier. IEEE Journal of Solid-State Circuits, 24(2):487-493, April 1989.
Tero Säntti and Jouni Isoaho. Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. In Proc. International Symposium on Circuits and Systems, volume 4, pages 194-197, 2001.
H. Sato. On multiple-valued logical functions realized by asynchronous sequential circuits. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, E79-A(4):513-519, April 1996.
G. Saucier. Encoding of asynchronous sequential networks. IEEE Transactions on Electronic Computers, EC-16:365-369, June 1967.
G. Saucier. State assignment of asynchronous sequential machines using graph techniques. IEEE Transactions on Computers, 21:282-288, March 1972.
Milton Sawasaki, Chantal Ykman-Couvreur, and Bill Lin. Externally hazard-free implementations of asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, June 1995.
Milton H. Sawasaki, Chantal Ykman-Couvreur, and Bill Lin. Externally hazard-free implementations of asynchronous control circuits. IEEE Transactions on Computer-Aided Design, 16(8):835-848, August 1997.
M. H. Sawasaki. General Hazard-Free Synthesis of Asynchronous Circuits. PhD thesis, Katholieke Universiteit Leuven, February 1994.
D. H. Sawin and G. K. Maki. Asynchronous sequential machines designed for fault detection. IEEE Transactions on Computers, C-23(3):239-249, March 1974.
J. Saxena and D. K. Pradhan. Design for testability of asynchronous sequential circuits. In Proc. International Conf. Computer Design (ICCD), pages 518-522. IEEE Computer Society Press, October 1993.
Volker Schöber and Thomas Kiel. An asynchronous scan path concept for micropipelines using the bundled data convention. In Proc. International Test Conference, October 1996.
Huub M. J. L. Schols. A formalisation of the foam rubber wrapper principle. Master's thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1985.
Huub Schols. Delay-insensitive Communication. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, December 1992.
Thomas Schumann, Ulrich Jagdhold, and Heinrich Klar. A power management for self-timed CMOS circuits (FLAGMAN) and investigations on the impact of technology scaling. In Power Driven Microarchitecture Workshop, June 1998.
U. Schwiegelshohn and L. Thiele. Properties of change diagrams. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 77-92. Kluwer Academic Publishers, March 2000.
C-J. Seger and J.A. Brzozowski. An optimistic ternary simulation of gate races. Theoretical Computer Science, 61(1):49-66, October 1988.
C-J. Seger and J.A. Brzozowski. Generalized ternary simulation of sequential circuits. Informatique Theorique et Applications, 28(3-4):159-186, 1994.
C.-J. Seger. On the existence of speed-independent circuits. Research Report CS-87-63, Computer Science Dept., Univ. of Waterloo, Canada, November 1987.
C.-J. Seger. Models and algorithms for race analysis in asynchronous circuits. Research Report (PhD thesis) CS-88-22, Computer Science Dept., Univ. of Waterloo, Canada, May 1988.
C-J. Seger. On the existence of speed-independent circuits. Theoretical Computer Science, 86(2):343-364, 1991.
John Segers and Jo C. Ebergen. Design and analysis of up-down counters. Science of Computer Programming, 27(2):185-204, 1996.
J. P. L. Segers. The design and analysis of asynchronous up-down counters. Master's thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, June 1993.
Charles L. Seitz and Wen-King Su. A family of routing and communication chips based on the mosaic. In Proc. of 1993 Symposium on Research on Integrated Systems, pages 320-337. MIT Press, January 1993.
Charles L. Seitz. Asynchronous machines exhibiting concurrency, 1970. Record of the Project MAC Concurrent Parallel Computation.
Charles L. Seitz. Self-timed VLSI systems. In Charles L. Seitz, editor, Proceedings of the 1st Caltech Conference on Very Large Scale Integration, pages 345-355, Pasadena, CA, January 1979. Caltech C.S. Dept.
Charles L. Seitz. Ideas about arbiters. Lambda, 1(1, First Quarter):10-14, 1980.
Charles L. Seitz. System timing. In Carver A. Mead and Lynn A. Conway, editors, Introduction to VLSI Systems, chapter 7. Addison-Wesley, 1980.
Jakov N. Seizovic. Pipeline synchronization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 87-96, November 1994. (PostScript)
Peter Selinger. First-order axioms for asynchrony. In Antoni Mazurkiewicz and Józef Winkowski, editors, CONCUR97: Concurrency Theory, volume 1243 of Lecture Notes in Computer Science, pages 376-390. Springer-Verlag, 1997.
A. Semenov and A. Yakovlev. Event-based framework for verification of of high-level models of asynchronous circuits. Technical Report TR 487, Dept. of Computing Science, Univ. of Newcastle upon Tyne, 1994.
A. Semenov and A. Yakovlev. Combining partial orders and symbolic traversal for efficient verification of asynchronous circuits. In Asia-Pacific Conference on Hardware Description Languages (APCHDL), pages 567-573, 1995.
Alexei Semenov and Alex Yakovlev. Verification of asynchronous circuits using time Petri-net unfolding. In Proc. ACM/IEEE Design Automation Conference, pages 59-63, 1996.
A. Semenov, A. M. Koelmans, L. Lloyd, and A. Yakovlev. Designing an asynchronous processor using Petri nets. IEEE Micro, 17(2):54-64, 1997.
Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Peña, and Jordi Cortadella. Synthesis of speed-independent circuits from STG-unfolding segment. In Proc. ACM/IEEE Design Automation Conference, pages 16-21, 1997. (PostScript)
Alex Semenov, Alexandre Yakovlev, Enric Pastor, Marco Peña, Jordi Cortadella, and Luciano Lavagno. Partial order based approach to synthesis of speed-independent circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 254-265. IEEE Computer Society Press, April 1997. (PostScript)
G. Semeraro, D. H. Albonesi, G. Magklis, M. L. Scott, S. G. Dropsho, and S. Dwarkadas. Hiding synchronization delays in GALS processor microarchitecture. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 159-169. IEEE Computer Society Press, April 2004.
Yaron Semiat and Ran Ginosar. Timing measurements of synchronization circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 68-77. IEEE Computer Society Press, May 2003.
E. Senn and B. Zavidovique. Hazard-free self-timed design: methodology and application to asynchronous routing in an heterogeneous parallel machine. Journal of VLSI Signal Processing, 22(3), October 1999.
E. Senn and B. Zavidovique. Self-timed design: An avenue to complex computer systems. In Proc. Hawaii International Conf. System Sciences, January 1999.
E. Senn and B. Zavidovique. Designing a low-power (self-timed) router for a MIMD computer. In Proc. International Symposium on Circuits and Systems, volume 5, pages 737-740, May 2000.
E. Senn and B. Zavidovique. Examples of image processing to benefit from an asynchronous implementation. In Proceedings of Fifth IEEE International Workshop on Computer Architectures for Machine Perception, pages 270-279, September 2000.
E. Senn. Self-timed design: methodology and application to the building of a communication processor for a parallel machine. PhD thesis, Paris XI University, 1998.
E. M. Sentovich, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A system for sequential circuit synthesis. Technical report, U.C. Berkeley, May 1992. (PostScript)
M. Shams, J. Ebergen, and M. Elmasry. A comparison of CMOS implementations of an asynchronous circuits primitive: the C-element. In International Symposium on Low Power Electronics and Design, pages 93-96, August 1996.
Maitham Shams, Jo C. Ebergen, and Mohamed I. Elmasry. Optimizing CMOS implementations of the C-element. In Proc. International Conf. Computer Design (ICCD), pages 700-705, October 1997.
Maitham Shams, Jo C. Ebergen, and Mohamed I. Elmasry. Modeling and comparing CMOS implementations of the C-element. IEEE Transactions on VLSI Systems, 6(4):563-567, December 1998.
Maitham Shams. Modeling and Optimization of CMOS Logic Circuits with Application to Asynchronous Design. PhD thesis, Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada, May 1999. (PostScript)
D. Shang, F. Xia, and A. Yakovlev. Asynchronous circuit synthesis via direct translation. In Proc. International Symposium on Circuits and Systems, volume 3, pages 369-372, May 2000.
D. Shang, F. Xia, and A. Yakovlev. An implementation of a three-slot asynchronous communication mechanism using self-timed circuits. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 37-44, July 2000.
Devang G. Sheth, Sheran Alles, and Syed M. Mahmud. A single-chip hig-speed M-to-B arbiter for multiple bus multiprocessor systems. In Proc. of the Midwest Symposium on Circuits and Systems, pages 284-287, 1993.
R. Shidhar. Asynchronous design techniques. In Proc. of Fifth Annual IEEE International ASIC Conference and Exhibit, pages 296-300, 1992.
Ming-Der Shieh, Chin-Long Wey, and P. David Fisher. Model of asynchronous finite state machines and their pipelined structures. In Proc. of the Midwest Symposium on Circuits and Systems, pages 659-662, 1992.
M.-D. Shieh, C.-L. Wey, and P. D. Fisher. Fault effects in asynchronous sequential logic circuits. IEE Proceedings, Computers and Digital Techniques, 140(6):327-332, November 1993.
Ming-Der Shieh, Chin-Long Wey, and P. David Fisher. A scan design for asynchronous sequential logic circuits using SR-latches. In Proc. of the Midwest Symposium on Circuits and Systems, pages 1300-1303, 1993.
Ming-Der Shieh, Wann-Shyang Ju, and Ming-Hwa Sheu. Low-power state assignment for asynchronous finite state machines. In Proc. of the Midwest Symposium on Circuits and Systems, volume 3, pages 1325-1328, 1997.
M.-D. Shieh. Design and Synthesis of Testable Asynchronous Sequential Logic Circuits. PhD thesis, Dept. of Electrical Engineering, Michigan State University, May 1993.
Myoung-Cheol Shin, Se-Hyeon Kang, and In-Cheol Park. An area-efficient iterative modified-Booth multiplier based on self-timed clocking. In Proc. International Conf. Computer Design (ICCD), pages 511-512, November 2001.
N. Shintel and M. Yoeli. Synthesis of modular networks from Petri-net specifications. Technical Report 743, Dept. Comp. Science, Technion, Haifa, Israel, 1992.
Philip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, and Marly Roncken. DUDES: A fault abstraction and collapsing framework for asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 73-82. IEEE Computer Society Press, April 2000.
Polly Siegel and Giovanni De Micheli. Decomposition methods for library binding of speed-independent asynchronous designs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 558-565, November 1994.
P. Siegel, G. De Micheli, and D. Dill. Automatic technology mapping for generalized fundamental-mode asynchronous designs. In Proc. ACM/IEEE Design Automation Conference, pages 61-67, June 1993.
Polly S. K. Siegel. Automatic Technology Mapping for Asynchronous Designs. PhD thesis, Stanford University, February 1995.
S. Silver. True concurrency in models of asynchronous circuit behavior. Master's thesis, Department of Computer Science, University of Waterloo, Waterloo, Ontario, Canada, January 1999. (PostScript)
H. R. Simpson. Four-slot fully asynchronous communication mechanism. IEE Proceedings, Computers and Digital Techniques, 137(1):17-30, January 1990.
H. R. Simpson. Correctness analysis for class of asynchronous communication mechanisms. IEE Proceedings, Computers and Digital Techniques, 139(1):35-49, January 1992.
H. R. Simpson. New algorithms for asynchronous communication. IEE Proceedings, Computers and Digital Techniques, 144(4):227-231, July 1997.
H. R. Simpson. Role model analysis of an asynchronous communication mechanism. IEE Proceedings, Computers and Digital Techniques, 144(4):232-240, July 1997.
J. C. Sims and H. J. Gray. Design criteria for autosynchronous circuits. In Proc. Eastern Joint Computer Conf. (AFIPS), volume 14, pages 94-99, December 1958.
Tze-Yee Sin, E.M.C. Wong, and I.C.C. Jong. A 1.6-GHz 16x16b asynchronous pipelined multiplier. In Proc. of the Midwest Symposium on Circuits and Systems, volume 1, pages 336-339, 2001.
Chiu sing Choy, Jan Butas, Juraj Povazanec, and Cheong fat Chan. A new control circuit for asynchronous micropipelines. IEEE Transactions on Computers, 50(9):993-998, September 2001.
M. Singh and S. Nowick. Synthesis-for-initializability of asynchronous sequential machines. In Proc. International Test Conference, October 1996.
Montek Singh and Steven M. Nowick. Fine-grain pipelined asynchronous adders for high-speed DSP applications. In Proceedings of the IEEE Computer Society Workshop on VLSI, pages 111-118. IEEE Computer Society Press, April 2000.
Montek Singh and Steven M. Nowick. High-throughput asynchronous pipelines for fine-grain dynamic datapaths. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 198-209. IEEE Computer Society Press, April 2000.
Montek Singh and Steven M. Nowick. MOUSETRAP: Ultra-high-speed transition-signaling asynchronous pipelines. In Proc. International Conf. Computer Design (ICCD), pages 9-17, November 2001.
Montek Singh, Jose A. Tierno, Alexander Rylyakov, Sergey Rylov, and Steven M. Nowick. An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 84-95, April 2002.
N. P. Singh. A design methodology for self-timed systems. Master's thesis, Laboratory for Computer Science, Massachucetts Institute of Technology, February 1981. MIT/LCS/TR-258.
V. W. Y. Sit, C. S. Choy, and C. F. Chan. Use of current sensing technique in designing asynchronous static RAM for self-timed systems. Electronics Letters, 33(8):667-668, 1997.
Vincent Wing-Yun Sit, Chiu-Sing Choy, and Cheong-Fat Chan. A four-phase handshaking asynchronous static RAM design for self-timed systems. IEEE Journal of Solid-State Circuits, 34(1):90-96, January 1999.
Pui-Lam Siu, Chiu-Sing Choy, J. Butas, and C.F. Chan. A low power asynchronous DES. In Proc. International Symposium on Circuits and Systems, volume 4, pages 538-541, 2001.
Pui-Lam Siu, Chiu-Sing Choy, Cheong-Fat Chan, and Kong-Pang Pun. A contactless smartcard designed with asynchronous circuit technique. In Proc. European Solid-State Circuits Conference (ESSCIRC), 2003.
Allen E. Sjogren and Chris J. Myers. Interfacing synchronous and asynchronous modules within a high-speed pipeline. In Advanced Research in VLSI, pages 47-61, September 1997.
Allen E. Sjogren and Chris J. Myers. Interfacing synchronous and asynchronous modules within a high-speed pipeline. IEEE Transactions on VLSI Systems, 8(5):573-583, October 2000. (PDF)
E. van de Sluis and A. F. van der Stappen. Performance analysis of VLSI programs. In Proceedings CSN 91, Computing Science in The Netherlands, volume 2, pages 499-513. SION, November 1991.
Ross Smith and Michiel Ligthart. High-level design for asynchronous logic. In Proc. of Asia and South Pacific Design Automation Conference, pages 431-436, February 2001.
J. R. Smith and C. H. Roth. Analysis and synthesis of asynchronous sequential network using edge-sensitive flip-flops. IEEE Transactions on Computers, 20:847-855, 1971.
Scott F. Smith and Amy E. Zwarico. Provably correct synthesis of asynchronous circuits. In Jørgen Staunstrup and Robin Sharp, editors, Designing Correct Circuits, volume A-5 of IFIP Transactions, pages 237-260. Elsevier Science Publishers, 1992.
Scott F. Smith and Amy E. Zwarico. Correct compilation of specifications to deterministic asynchronous circuits. In Correct Hardware Design and Verification Methods (CHARME '93), volume 683 of Lecture Notes in Computer Science, pages 179-190. Springer-Verlag, May 1993.
Scott F. Smith and Amy E. Zwarico. Correct compilation of specifications to deterministic asynchronous circuits. Formal Methods in System Design, 7(3):156-226, November 1995.
R. Smith, K. Fant, D. Parker, R. Stephani, and C. Y. Wang. An asynchronous 2-D discrete cosine transform chip. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 224-233, 1998.
S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. Delay-insensitive gate-level pipelining. Integration, the VLSI journal, 30(2):103-131, 2001. (PDF)
S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. Speedup of delay-insensitive digital systems using null cycle reduction. In Proceedings of 10th International Workshop on Logic and Synthesis, pages 185-189, June 2001. (PDF)
S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson. Null convention multiply and accumulate unit with conditional rounding, scaling, and saturation. Journal of Systems Architecture, 47(12):977-998, February 2003. (PDF)
R. J. Smith. Generation of internal state assignments for large asynchronous sequential machines. IEEE Transactions on Computers, 23:924-932, September 1974.
S. C. Smith. Gate and Throughput Optimizations for Null Convention Self-timed Digital Circuits. PhD thesis, Department of Electrical and Computer Engineering, University of Central Florida, 2001. (PDF)
Jan L. A. van de Snepscheut. Deriving circuits from programs. In Randal Bryant, editor, Proceedings of Third Caltech Conference on VLSI, pages 241-256. Computer Science Press, 1983.
Jan L. A. van de Snepscheut. Trace Theory and VLSI Design, volume 200 of Lecture Notes in Computer Science. Springer-Verlag, 1985.
Gerald E. Sobelman and Karl Fant. CMOS circuit design of threshold gates with hysteresis. In Proc. International Symposium on Circuits and Systems, pages 61-64, June 1998.
D. Sokolov, A. Bystrov, and A. Yakovlev. STG optimisation in the direct mapping of asynchronous circuits. In Proc. Design, Automation and Test in Europe (DATE). IEEE Computer Society Press, March 2003.
Christos Sotiriou. Implementing asynchronous circuits using a conventional EDA tool-flow. In Proc. ACM/IEEE Design Automation Conference, June 2002.
Jens Sparsø and Steve Furber, editors. Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, 2001.
Jens Sparsø and Jørgen Staunstrup. Delay-insensitive multi-ring structures. Integration, the VLSI journal, 15(3):313-340, October 1993. (PostScript)
Jens Sparsø and Jørgen Staunstrup. Design and performance analysis of delay insensitive multi-ring structures. In Proc. Hawaii International Conf. System Sciences, volume I, pages 349-358. IEEE Computer Society Press, January 1993.
Jens Sparsø, Jørgen Staunstrup, and Michael Dantzer-Sørensen. Design of delay insensitive circuits using multi-ring structures. In Proc. European Design Automation Conference (EURO-DAC), pages 15-20, Hamburg, Germany, September 1992. IEEE Computer Society Press.
J. Sparsø, C. D. Nielsen, L. S. Nielsen, and J. Staunstrup. Design of self-timed multipliers: A comparison. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 165-179. Elsevier Science Publishers, 1993. (PostScript)
Robert F. Sproull and Ivan E. Sutherland. Asynchronous Systems. Sutherland, Sproull and Associates, Palo Alto, 1986. Vol. I: Introduction, Vol. II: Logical effort and asynchronous modules, Vol. III: Case studies.
Robert F. Sproull, Ivan E. Sutherland, and Charles E. Molnar. The counterflow pipeline processor architecture. IEEE Design & Test of Computers, 11(3):48-59, Fall 1994. (PostScript)
Nattha Sretasereekul and Takashi Nanya. Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. In Proc. of Asia and South Pacific Design Automation Conference, pages 437-442, February 2001.
N. Starodoubtsev, A. Bystrov, and A. Yakovlev. Semi-modular latch chains for asynchronous circuit design. In Power and Timing Modeling, Optimization and Simulation (PATMOS), volume 1918 of Lecture Notes in Computer Science, pages 168-177, September 2000.
N. Starodoubtsev, M. Goncharov, I. Klotchkov, and A. Smirnov. Synthesis of asynchronous interface circuits by STG refinement. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 65-74, July 2000.
Nikolai Starodoubtsev, Sergei Bystrov, and Alex Yakovlev. Monotonic circuits with complete acknowledgement. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 98-108. IEEE Computer Society Press, May 2003.
Jørgen Staunstrup and Mark Greenstreet. Designing delay insensitive circuits using synchronized transitions. In Luc J.M. Claesen, editor, Formal VLSI Specification and Synthesis. VLSI Design Methods, volume 1, pages 209-226. Elsevier Science Publishers, 1990. (PostScript)
Jørgen Staunstrup, S. Garland, and J. Guttag. Localized verification of circuit descriptions. In Proceedings of the Workshop on Automatic Verification Methods for Finite State Systems, volume 407 of Lecture Notes in Computer Science. Springer-Verlag, 1989.
Jørgen Staunstrup. A Formal Approach to Hardware Design, chapter 7. Kluwer Academic Publishers, 1994. Ch. 7: Self-Timed Circuits.
Ken Stevens, Ran Ginosar, and Shai Rotem. Relative timing. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 208-218, April 1999.
Ken Stevens, Shai Rotem, Steven M. Burns, Jordi Cortadella, Ran Ginosar, Michael Kishinevsky, and Marly Roncken. CAD directions for high performance asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, pages 116-121, 1999.
K. S. Stevens, S. Rotem, R. Ginosar, P. Beerel, C. J. Myers, K. Y. Yun, R. Koi, C. Dike, and M. Roncken. An asynchronous instruction length decoder. IEEE Journal of Solid-State Circuits, 36(2):217-228, February 2001. (PostScript) (PDF)
Kenneth S. Stevens. Practical Verification and Synthesis of Low Latency Asynchronous Systems. PhD thesis, Dept. of Computer Science, University of Calgary, Canada, September 1994. (PostScript)
Kenneth S. Stevens. Energy and performance models for clocked and asynchronous communication. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 56-66. IEEE Computer Society Press, May 2003.
Marco Storto and Roberto Saletti. Time-multiplexed dual-rail protocol for low-power delay-insensitive asynchronous communication. In Anne-Marie Trullemans-Anckaert and Jens Sparsø, editors, Power and Timing Modeling, Optimization and Simulation (PATMOS), pages 127-136, October 1998.
Bret Stott, Dave Johnson, and Venkatesh Akella. Asynchronous 2-D discrete cosine transform core processor. In Proc. International Conf. Computer Design (ICCD), pages 380-385. IEEE Computer Society Press, 1995.
M. J. Stucki and Jr. J. R. Cox. Synchronization strategies. In Charles L. Seitz, editor, Proceedings of the First Caltech Conference on Very Large Scale Integration, pages 375-393, 1979.
Mishell J. Stucki, Severo M. Ornstein, and Wesley A. Clark. Logical design of macromodules. In AFIPS Conference Proceedings: 1967 Spring Joint Computer Conference, volume 30, pages 357-364, Atlantic City, NJ, 1967. Academic Press.
Alfred K. Susskind. A technique for making asynchronous sequential machines readily testable. In Proc. International Test Conference, pages 842-846. IEEE Computer Society Press, 1984.
Ivan E. Sutherland and Jo Ebergen. Computers without clocks. Scientific American, 287(2), August 2002.
Ivan Sutherland and Scott Fairbanks. GasP: A minimal FIFO control. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 46-53. IEEE Computer Society Press, March 2001.
Ivan Sutherland and Jon Lexau. Designing fast asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 184-193. IEEE Computer Society Press, March 2001.
Ivan E. Sutherland, Charles E. Molnar, Robert F. Sproull, and J. Craig Mudge. The trimosbus. In Charles L. Seitz, editor, Proceedings of the First Caltech Conference on Very Large Scale Integration, pages 395-427, 1979.
Ivan Sutherland, Bob Sproull, and David Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, Inc., 1999.
Ivan E. Sutherland. Micropipelines. Communications of the ACM, 32(6):720-738, June 1989.
Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, and Hisanori Hamano. A floating-point divider using redundant binary circuits and an asynchronous clock scheme. In Proc. International Conf. Computer Design (ICCD), pages 685-689, October 1997.
Christer Svensson and Jiren Yuan. A 3-level asynchronous protocol for a differential two-wire communication link. IEEE Journal of Solid-State Circuits, 29(9):1129-1132, September 1994.
N. Tabrizi, K. Eshraghian, and M. J. Liebelt. Dynamic hazards and speed independent delay model. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
N. Tabrizi, M. J. Liebelt, and K. Eshraghian. Delay hazards in complex gate based speed independent VLSI circuits. In Proc. of the Great Lakes Symposium on VLSI, pages 266-271, March 1996.
Nozar Tabrizi, Michael J. Liebelt, and Kamran Eshraghian. A tabular method for guard strengthening, symmetrization, and operator reduction for Martin's asynchronous design methodology. IEEE Transactions on Computers, 46(9):1050-1054, September 1997.
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, and Takashi Nanya. TITAC-2: An asynchronous 32-bit microprocessor based on scalable-delay-insensitive model. In Proc. International Conf. Computer Design (ICCD), pages 288-294, October 1997.
Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, and Tadao Nakamura. Automated design of wave pipelined multiport register files. In Proc. of Asia and South Pacific Design Automation Conference, pages 197-202, February 1998.
Hidehiro Takata, Shinji Komori, Toshiyuki Tamura, Fumiyasu Asai, Hisakazu Satoh, Takio Ohno, Takeshi Tokuda, Hiroaki Nishikawa, and Hiroaki Terada. A 100-mega-access per second matching memory for a data-driven microprocessor. IEEE Journal of Solid-State Circuits, 25(1):95-99, February 1990.
Y. K. Tan and Y. C. Lim. Self-timed precharge latch. In Proc. International Symposium on Circuits and Systems, volume 1, pages 566-569, May 1990.
Y. K. Tan and Y. C. Lim. Self-timed system design technique. Electronics Letters, 26(5):284-286, March 1990.
Y. K. Tan, Y. C. Lim, and H. W. Leong. Speed-independent circuit design using net-theoretic techniques. In Proc. International Symposium on Circuits and Systems, volume 6, pages 2973-2976, 1992.
S.-Y. Tan, S. B. Furber, and W.-F. Yen. The design of an asynchronous VHDL synthesizer. In Proc. Design, Automation and Test in Europe (DATE). IEEE Computer Society Press, February 1998.
C. J. Tan. State assignments for asynchronous sequential machines. IEEE Transactions on Computers, 20(4):382-391, April 1971.
Tin-Yau Tang, Chiu-Sing Choy, Jan Butas, and Cheong-Fat Chan. An ALU design using a novel asynchronous pipeline architecture. In Proc. International Symposium on Circuits and Systems, May 2000.
Tin-Yau Tang, Chiu-Sing Choy, Pui-Lam Siu, and Cheon-Fat Chan. Design of self-timed asynchronous Booth's multiplier. In Proc. of Asia and South Pacific Design Automation Conference, pages 15-16, 2000.
M. A. Tapia. Synthesis of asynchronous sequential systems using boolean calculus. In Proceedings of the 14th Asimolar Conference on Circuits, Systems and Computers, pages 205-209, November 1980.
A. Taubin, A. Kondratyev, J. Cortadella, and L. Lavagno. Behavioral transformations to increase the noise immunity of asynchronous specifications. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 36-47, April 1999.
G. S. Taylor and G. M. Blair. Reduced complexity two-phase micropipeline latch controller. In Proc. European Solid-State Circuits Conference (ESSCIRC), September 1997.
George S. Taylor and Gerard M. Blair. Reduced complexity two-phase micropipeline latch controller. IEEE Journal of Solid-State Circuits, 33(10):1590-1593, October 1998.
George Taylor, Simon Moore, Steev Wilcox, and Peter Robinson. An on-chip dynamically recalibrated delay line for embedded self-timed systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 45-51, April 2000.
Chen Kong Teh and Y. Okabe. New BSFQ circuit designs with wide margins. IEEE Transactions on Applied Superconductivity, 11(1):970-973, 2001.
Chen Kong Teh and Y. Okabe. A novel global self-timing methodology for BSFQ circuits. IEEE Transactions on Applied Superconductivity, 13(2):543-546, 2003.
John Teifel and Rajit Manohar. A high-speed clockless serial link transceiver. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 151-161. IEEE Computer Society Press, May 2003.
John Teifel and Rajit Manohar. Static tokens: Using dataflow to automate concurrent pipeline synthesis. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 17-27. IEEE Computer Society Press, April 2004.
John Teifel, David Fang, David Biermann, Clint Kelly, and Rajit Manohar. Energy-efficient pipelines. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 23-33, April 2002.
S. Temple and S. B. Furber. On-chip timing reference for self-timed microprocessor. Electronics Letters, 36(11):942-943, 2000.
Hiroaki Terada, Makoto Iwata, Souichi Miyata, and Shinji Komori. Superpipelined dynamic data-driven VLSI processors. In Advanced Topics in Dataflow Computing and Multithreading, pages 75-85. IEEE Computer Society Press, 1995.
Hiroaki Terada, Souichi Miyata, and Makoto Iwata. DDMP's: Self-timed super-pipelined data-driven multimedia processors. Proceedings of the IEEE, 87(2):282-296, February 1999.
M. Teramoto and F. Fukazawa. Test-pattern generation for circuits with asynchronous signals based on scan. In Proc. International Test Conference, October 1996.
Robert A. Thacker and Chris J. Myers. Synthesis of timed circuits using BDDs. In Proc. International Workshop on Logic Synthesis, 1997.
R. A. Thacker, W. Belluomini, and C. J. Myers. Timed circuit synthesis using implicit methods. In Proc. International Conference on VLSI Design, pages 181-188, 1999.
M. Theobald and S. M. Nowick. An implicit method for hazard-free two-level minimization. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 58-69, 1998.
Michael Theobald and Steven M. Nowick. Fast heuristic and exact algorithms for two-level hazard-free logic minimization. IEEE Transactions on Computer-Aided Design, 17(11):1130-1147, November 1998.
M. Theobald and S. M. Nowick. Transformations for the synthesis and optimization of asynchronous distributed control. In Proc. ACM/IEEE Design Automation Conference, June 2001.
Michael Theobald, Steven M. Nowick, and Tao Wu. Espresso-HF: A heuristic hazard-free minimizer for two-level logic. In Proc. ACM/IEEE Design Automation Conference, 1996.
G. Theodoropoulos and J. V. Woods. Building parallel distributed models for asynchronous computer architectures. In Proceedings of the World Transputer Congress 1994, pages 285-301, September 1994. (PostScript)
G. Theodoropoulos and J. V. Woods. Distributed simulation of asynchronous computer architectures: The program driven conservative approach. In Proceedings of the European Simulation Symposium 1994, Volume 2, pages 230-234, October 1994. (PostScript)
G. Theodoropoulos and J. V. Woods. Analyzing the timing error in distributed simulations of asynchronous computer architectures. In Proceedings of the Eurosim Congress, pages 529-534, September 1995. (PostScript)
G. Theodoropoulos and J. V. Woods. Dealing with time modelling problems in parallel models of asynchronous computer architectures. In Proceedings of the World Transputer Congress, pages 457-472, September 1995. (PostScript)
G. K. Theodoropoulos, G. K. Tsakogiannis, and J. V. Woods. Occam: an asynchronous hardware description language? In Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology, pages 249-256, September 1997.
G. Theodoropoulos. Strategies for the Modelling and Simulation of Asynchronous Computer Architectures. PhD thesis, Department of Computer Science, University of Manchester, 1995. (PostScript)
M. A. Thornton, K. Fazel, R. B. Reese, and C. Traver. Generalized early evaluation in self-timed circuits. In Proc. Design, Automation and Test in Europe (DATE), pages 255-259, March 2002.
José A. Tierno and Prabhakar Kudva. Asynchronous transpose-matrix architectures. In Proc. International Conf. Computer Design (ICCD), October 1997.
José A. Tierno and Alain J. Martin. Low-energy asynchronous memory design. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 176-185, November 1994. (PostScript)
José A. Tierno, Alain J. Martin, Drazen Borkovic, and Tak Kwan Lee. An asynchronous microprocessor in Gallium Arsenide. Technical Report CS-TR-93-38, California Institute of Technology, 1993. (PostScript)
José A. Tierno, Alain J. Martin, Drazen Borkovic, and Tak Kwan Lee. A 100-MIPS GaAs asynchronous microprocessor. IEEE Design & Test of Computers, 11(2):43-49, 1994.
J. Tierno, R. Manohar, and A. Martin. Energy and entropy measures for low power design. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. (PostScript)
Jose Tierno, Alexander Rylyakov, Sergey Rylov, Montek Singh, Paul Ampadu, Steven Nowick, Michael Immediato, and Sudhir Gowda. A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces. In International Solid State Circuits Conference, February 2002.
J. A. Tierno. Designing asynchronous circuits in Gallium Arsenide. Technical Report CS-TR-92-19, California Institute of Technology, 1992. (PostScript)
José A. Tierno. An Energy-Complexity Model for VLSI Computations. PhD thesis, California Institute of Technology, 1995. Caltech technical report CS-TR-95-02. (PostScript)
R. F. Tinder, R. I. Klaus, and J. A. Snodderley. High-speed microprogrammable asynchronous controller modules. IEEE Transactions on Computers, 43(10):1226-1232, October 1994.
M. B. Tosic, M. K. Stojcev, D. M. Maksimovic, and G. L. Djordjevic. Speed-independent bit-serial multiplier. In Proceedings of International Conference on Microelectronics, volume 2, pages 829-834, 1995.
M. B. Tosic, M. K. Stojcev, and G. L. Djordjevic. Asynchronous controller for token-ring mutual exclusion: delay-insensitive arbiter cell. In Proc. of the 21st International Conference on Microelectronics, pages 819-822, September 1997.
M. B. Tosic, M. K. Stojcev, and G. L. Djordjevic. Asynchronous controller for token-ring mutual exclusion: ring design. In Proc. of the 21st International Conference on Microelectronics, pages 823-826, September 1997.
C. A. Tracer. Design for Testability Techniques for Globally-Asynchronous Locally-Synchronous Systems. PhD thesis, University of Virginia, 1988.
J. H. Tracey. Internal state assignments for asynchronous sequential machines. IEEE Transactions on Electronic Computers, EC-15:551-560, August 1966.
P.K. Tsang, C.C. Cheung, K.H. Leung, T.K. Lee, and P.H.W. Leong. MSL16A: an asynchronous Forth microprocessor. In Proceedings of the IEEE Region 10 Conference (TENCON99), pages 1079-1082, 1999.
J. M. C. Tse and D. P. K. Lun. ASYNMPU: a fully asynchronous CISC microprocessor. In Proc. International Symposium on Circuits and Systems, volume 3, pages 1816-1819, June 1997.
Sunan Tugsinavisut and Peter A. Beerel. Control circuit templates for asynchronous bundled-data pipelines. In Proc. Design, Automation and Test in Europe (DATE), page 1098, March 2002.
Johanna Tuominen, Pasi Liljeberg, and Jouni Isoaho. Self-timed approach for reducing on-chip switching noise. In IFIP International Conference on VLSI SoC, December 2003.
Susan P. Tyerman and Peter J. Ashenden. High level synthesis of asynchronous digital systems. In Alex Yakovlev and Reinder Nouta, editors, Asynchronous Interfaces: Tools, Techniques, and Implementations, pages 7-11, July 2000.
Jan Tijmen Udding and Tom Verhoeff. The mathematics of directed specifications. Technical Report WUCS-88-20, Dept. of C.S., Washington Univ., St. Louis, MO, June 1988.
Jan Tijmen Udding. Classification and Composition of Delay-Insensitive Circuits. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1984.
Jan Tijmen Udding. A formal model for defining and classifying delay-insensitive circuits. Distributed Computing, 1(4):197-204, 1986.
Jan Tijmen Udding. ACiD-WG workshop. Technical Report CSN 9602, University of Groningen, Dept. of Comp. Science, 1996.
S. H. Unger. Asynchronous Sequential Switching Circuits. Wiley-Interscience, John Wiley & Sons, Inc., New York, 1969.
S. H. Unger. Asynchronous sequential switching circuits with unrestricted input changes. In Annual Symposium on Switching and Automata Theory, pages 114-121. IEEE Computer Society Press, 1970.
Stephen H. Unger. Asynchronous sequential switching circuits with unrestricted input changes. IEEE Transactions on Computers, 20(12):1437-1444, December 1971.
Stephen H. Unger. Self-synchronizing circuits and nonfundamental mode operation. IEEE Transactions on Computers, 26(3):278-281, March 1977.
S. H. Unger. A building block approach to unclocked systems. In Proc. Hawaii International Conf. System Sciences, volume I. IEEE Computer Society Press, January 1993.
Stephen H. Unger. Hazards, critical races, and metastability. IEEE Transactions on Computers, 44(6):754-768, June 1995.
Stephen H. Unger. The Essence of Logic Circuits. IEEE Press, second edition, 1997.
Stephen H. Unger. Reducing power dissipation, delay, and area in logic circuits by narrowing transistors. IEEE Design & Test of Computers, 20(6):18-24, 2003.
R. Unnikrishnan and A. Gupta. Self-timed system design technique. Electronics Letters, 26(5):284-286, March 1990.
V. Vakilotojar and P. A. Beerel. RTL verification of asynchronous and heterogeneous systems using symbolic model checking. Integration, the VLSI journal, 24(1):19-36, December 1997.
V. Vakilotojar and P. A. Beerel. RTL verification of asynchronous and heterogeneous systems using symbolic model checking. In Proc. of Asia and South Pacific Design Automation Conference, pages 181-188, January 1997.
M. Valencia, M. J. Bellido, J. L. Huertas, A. J. Acosta, and S. Sanchez-Solano. Modular asynchronous arbiter insensitive to metastability. IEEE Transactions on Computers, 44(12):1456-1461, December 1995.
P. Vanbekbergen, F. Catthoor, G. Goossens, and H. De Man. Optimized synthesis of asynchronous control circuits form graph-theoretic specifications. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 184-187. IEEE Computer Society Press, 1990.
P. Vanbekbergen, F. Catthoor, G. Goossens, and H. De Man. Time & area performant synthesis of asynchronous control circuits. In Proceedings of TAU 90, 1990.
P. Vanbekbergen, B. Lin, G. Goossens, and H. de Man. A generalized state assignment theory for transformations on signal transition graphs. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 112-117. IEEE Computer Society Press, November 1992.
Peter Vanbekbergen, Gert Goossens, Francky Catthoor, and Hugo J. De Man. Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. IEEE Transactions on Computer-Aided Design, 11(11):1426-1438, November 1992.
Peter Vanbekbergen, Gert Goossens, and Bill Lin. Modeling and synthesis of timed asynchronous circuits. In Proc. European Design Automation Conference (EURO-DAC), pages 460-465. IEEE Computer Society Press, September 1994.
Peter Vanbekbergen, Bill Lin, Gert Goossens, and Hugo de Man. A generalized state assignment theory for transformations on signal transition graphs. Journal of VLSI Signal Processing, 7(1/2):101-115, February 1994.
Peter Vanbekbergen, Chantal Ykman-Couvreur, Bill Lin, and Hugo de Man. A generalized signal transition graph model for specification of complex interfaces. In Proc. European Design and Test Conference, pages 378-384. IEEE Computer Society Press, 1994.
Peter Vanbekbergen, Albert Wand, and Kurt Keutzer. A design and validation system for asynchronous circuits. In Proc. ACM/IEEE Design Automation Conference, June 1995.
Peter Vanbekbergen. Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. PhD thesis, Catholic University of Leuven, September 1993.
W. S. VanScheik and R. F. Tinder. High speed externally asynchronous/internally clocked systems. IEEE Transactions on Computers, 46(7):824-829, July 1997.
W. S. VanScheik. Externally asynchronous/internally single and dual clocked systems. Master's thesis, Washington State University, May 1993.
V. Varshavsky and T.-A. Chu. Self-timing --- tools for hardware support of parallel, concurrent and event-driven process control. In First International Conference on Massively Parallel Computing Systems, pages 472-476, May 1994.
V. I. Varshavsky and V. B. Marakhovsky. Asynchronous control device design by net model behavior simulation. In J. Billington and W. Reisig, editors, Application and Theory of Petri Nets 1996, volume 1091 of Lecture Notes in Computer Science, pages 497-515. Springer-Verlag, June 1996.
Victor Varshavsky and Vyacheslav Marakhovsky. GALA (globally asynchronous - locally arbitrary) design. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 61-107. Springer-Verlag, 2002.
V. Varshavsky, V. Marakhovsky, and T.-A. Chu. Logical timing (global synchronization of asynchronous arrays. In The First International Symposium on Parallel Algorithm/Architecture Synthesis, pages 130-138, Aizu-Wakamatsu, Japan, March 1995.
V. Varshavsky, V. Marakhovsky, and R. Lashevsky. Critical view on the current sensor application for self-timing in VLSI systems. In Proc. of the VLSI'95 Conference, pages 743-750, Chiba, Japan, August 1995.
V. I. Varshavsky, V. B. Marakhovsky, and R. A. Lashevsky. Asynchronous interaction in massively parallel computing systems. In Proc. of the IEEE 1st International Conference on Algorithms and Architectures for Parallel Processing, volume 2, pages 481-492, 1995.
Victor I. Varshavsky, Vyacheslav B. Marakhovsky, and Vadim V. Smolensky. Designing self-timed devices using the finite automaton model. IEEE Design & Test of Computers, 12(1):14-23, Spring 1995.
V. Varshavsky, V. Marakhovsky, and M. Tsukisaka. Data-controlled delays in the asynchronous design. In Proc. International Symposium on Circuits and Systems, volume 4, pages 153-155, May 1996.
Victor I. Varshavsky. Hardware support of parallel asynchronous processes. Research Reports Series A, No. 2, Digital Systems Laboratory, Helsinki Univ. of Technology, Otaniemi, Otakaari 5 A, SF-02150 ESPOO 15, Finland, September 1987.
Victor I. Varshavsky, editor. Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems. Kluwer Academic Publishers, Dordrecht, The Netherlands, 1990.
Harry J.M. Veendrick. The behavior of flip-flops used as synchronizers and prediction of their failure rate. IEEE Journal of Solid-State Circuits, 15(2):169-176, 1980.
Tom Verhoeff. Encyclopedia of Delay-Insensitive Systems (EDIS). tt http://www.win.tue.nl/~edis/edis.html.
Tom Verhoeff and Huub M. J. L. Schols. Delay-insensitive directed trace structures satisfy the foam rubber wrapper postulate. Computing Science Notes 85/04, Dept. of Math. and C.S., Eindhoven Univ. of Technology, August 1985.
Tom Verhoeff. Notes on delay-insensitivity. Master's thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1985.
Tom Verhoeff. Delay-insensitive codes--an overview. Distributed Computing, 3(1):1-8, 1988.
Tom Verhoeff. Characterizations of delay-insensitive communication protocols. Computing Science Notes 89/06, Dept. of Math. and C.S., Eindhoven Univ. of Technology, May 1989.
Tom Verhoeff. The testing paradigm applied to network structure. Technical Report 94/10, Dept. of Math. and C.S., Eindhoven Univ. of Technology, 1994. (PDF)
Tom Verhoeff. A Theory of Delay-Insensitive Systems. PhD thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, May 1994. (PDF)
Tom Verhoeff. Analyzing specifications for delay-insensitive circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 172-183, 1998. (PDF)
Eric Verlind, Gjalt de Jong, and Bill Lin. Efficient partial enumeration for timing analysis of asynchronous systems. In Proc. ACM/IEEE Design Automation Conference, 1996.
Eric Verlind. Efficient Timing Analysis of Asynchronous Systems and Synchronous Communication Channels. PhD thesis, Katholieke Universiteit Leuven, September 1999.
Thomas Villiger, Hubert Käslin, Frank K. Gürkaynak, Stephan Oetiker, and Wolfgang Fichtner. Self-timed ring for globally-asynchronous locally-synchronous systems. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 141-150. IEEE Computer Society Press, May 2003.
P. Vingron. Coherent design of asynchronous circuits. IEE Proceedings, Computers and Digital Techniques, 130(6):190-202, 1983.
Serban E. Vlad. An asynchronous automata approach to the semantics of temporal logic. In The 8-th Symposium of Mathematics and its Applications, Politehnica University, Timisoara, 1999. (PostScript) (PDF)
Serban E. Vlad. Selected topics in asynchronous automata. In Analele universitatii din Oradea, Fascicola matematica, Tom VII, 1999. (PostScript) (PDF)
Serban E. Vlad. The delay-insensitivity, the hazard-freedom, the semi-modularity and the technical condition of good running of the discrete time asynchronous automata. In Analele universitatii din Oradea, Fascicola matematica, Tom VIII, 2001. (PostScript) (PDF)
Serban E. Vlad. On timed automata: the inertial delay buffer. In The 9-th Symposium of Mathematics and its Applications, Politehnica University, Timisoara, 2001. (PostScript) (PDF)
Serban E. Vlad. On the delays of the asynchronous circuits. In 6th WSEAS CSCC Multiconference, Crete Island, Greece, July 2002. (PostScript) (PDF)
Serban E. Vlad. Towards a mathematical theory of the delays of the asynchronous circuits. In Analele Universitatii din Oradea, Fascicola Matematica, Tom IX, 2002. (PostScript) (PDF)
Felipe M. G. Franca Vladimir C. Alves and Edson P. Granja. A BIST scheme for asynchronous logic. In Proc. of the Asian Test Symposium, 1998.
Walter Vogler and Ralf Wollowski. Decomposition in asynchronous circuit design. In J. Cortadella, A. Yakovlev, and G. Rozenberg, editors, Concurrency and Hardware Design, volume 2549 of Lecture Notes in Computer Science, pages 152-190. Springer-Verlag, 2002.
W. Vogler. Efficiency of asynchronous systems that communicate asynchronously. In Proc. of the International Conference on Application and Theory of Petri Nets, June 2000.
W. M. Waite. The production of completion signals by asynchronous, iterative networks. IEEE Transactions on Computers, 13(2):83-86, April 1964.
Jacqueline Walker and Antonio Cantoni. A new synchronizer design. IEEE Transactions on Computers, 45(11):1308-1311, November 1996.
A. Walker and P. K. Lala. An approach for self-timed synchronous CMOS circuit design. In Southwest Symposium on Mixed-Signal Design, pages 180-184, 1999.
W. Wang. An asynchronous two-dimensional self-correcting cellular automaton. PhD thesis, Boston University, 1991.
Donald F. Wann and Mark A. Franklin. Asynchronous and clocked control structures for VLSI based interconnection networks. IEEE Transactions on Computers, C-32(3):284-293, March 1983.
Sam Weber, Bard Bloom, and Geoffrey Brown. Compiling Joy to silicon. In Thomas Knight and John Savage, editors, Advanced Research in VLSI, pages 79-98. MIT Press, March 1992.
Gu-Yeon Wei and Mark Horowitz. A low power switching power supply for self-clocked systems. In International Symposium on Low Power Electronics and Design, pages 313-317, August 1996.
D. T. Weih and M. R. Greenstreet. Verification of speed-independent data-path circuits. IEE Proceedings, Computers and Digital Techniques, 143(5):295-300, September 1996.
S. Wendt. Using Petri nets in the design process for interacting asynchronous sequential circuits. In IFAC Symposium on Discrete Systems, volume 2, pages 130-138, 1976.
T. Werner and V. Akella. Counterflow pipeline-based dynamic instruction scheduling. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
T. Werner and V. Akella. Asynchronous processor survey. Computer (USA), 30(11):67-76, November 1997.
Tony Werner and Venkatesh Akella. An asynchronous superscalar architecture for exploiting instruction-level parallelism. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 140-151. IEEE Computer Society Press, March 2001.
Tony Werner. An Asynchronous Superscalar Processor for Exploiting Instruction-Level Parallelism. PhD thesis, Dept. of Electrical and Computer Engineering, Univ. of California Davis, 2000.
C.-L. Wey, M.-D. Shieh, and P. D. Fisher. ASCLScan: a scan design for asynchronous sequential logic circuits. In Proc. International Conf. Computer Design (ICCD). IEEE Computer Society Press, 1993.
C.-L. Wey, H. Wang, and C.-P. Wang. A self-timed redundant-binary number to binary number convertor for digital arithmetic processors. In Proc. International Conf. Computer Design (ICCD), pages 386-391. IEEE Computer Society Press, 1995.
Sterling R. Whitaker and Gary K. Maki. Pass-transistor asynchronous sequential circuits. IEEE Journal of Solid-State Circuits, 24(1):71-78, February 1989.
Rik van de Wiel. An operational semantics for the DI-algebra. Master's thesis, Dept. of Math. and C.S., Eindhoven Univ. of Technology, July 1992.
Rik van de Wiel. High-level test evaluation of asynchronous circuits. In Asynchronous Design Methodologies, pages 63-71. IEEE Computer Society Press, May 1995.
Ted E. Williams and Mark A. Horowitz. Bipolar circuit elements providing self-completion-indication. IEEE Journal of Solid-State Circuits, 25(1):309-312, January 1990.
Ted E. Williams and Mark A. Horowitz. A 160ns 54bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. In Peter Kornerup and David W. Matula, editors, Proceedings of the 10th IEEE Symposium on Computer Arithmetic, pages 210-217, 1991.
Ted E. Williams and Mark A. Horowitz. A zero-overhead self-timed 160ns 54b CMOS divider. IEEE Journal of Solid-State Circuits, 26(11):1651-1661, November 1991.
T. E. Williams and Klingsheim K. Self-timed circuit elements in GaAs. In Proceedings of the 13th Nordic Semiconductor Conference, pages 344-347, June 1988. Conference held in Stockhold, Sweden.
T. E. Williams, M. Horowitz, R. L. Alverson, and T. S. Yang. A self-timed chip for division. In Paul Losleben, editor, Advanced Research in VLSI, pages 75-95. MIT Press, 1987.
Ted Williams, Niteen Patkar, and Gene Shen. SPARC64: A 64-b 64-active-instruction out-of-order-execution MCM processor. IEEE Journal of Solid-State Circuits, 30(11):1215-1226, November 1995.
Ted E. Williams. Latency and throughput tradeoffs in self-timed asynchronous pipelines and rings. Technical Report CSL-TR-90-431, Stanford University, August 1990.
Ted E. Williams. Self-Timed Rings and their Application to Division. PhD thesis, Stanford University, June 1991.
Ted E. Williams. Analyzing and improving the latency and throughput performance of self-timed pipelines and rings. In Proc. International Symposium on Circuits and Systems, May 1992.
Ted E. Williams. Performance of iterative computation in self-timed rings. Journal of VLSI Signal Processing, 7(1/2):17-31, February 1994.
Anthony J. Winstanley and Mark R. Greenstreet. Temporal properties of self-timed rings. In Proc. 11th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME), September 2001.
Anthony J. Winstanley, Aurelien Garivier, and Mark R. Greenstreet. An event spacing experiment. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 47-56, April 2002.
Brian D. Winters and Mark R. Greenstreet. A negative-overhead, self-timed pipeline. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 37-46, April 2002.
Brian D. Winters and Mark R. Greenstreet. Surfing: a robust form of wave pipelining using self-timed circuit techniques. Microprocessors and Microsystems, 27(9):409-419, October 2003.
Anthony S. Wojcik and Kwang-Ya Fang. On the design of three-valued asynchronous modules. IEEE Transactions on Computers, 29(10):889-898, October 1980.
R. Wollowski and J. Beister. Precise Petri net modelling of critical races in asynchronous arbiters and synchronizers. In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 46-65, June 1998.
R. Wollowski and J. Beister. Comprehensive causal specification of asynchronous circuit behaviour: a generalized STG. In Proc. of the Workshop Hardware Design and Petri Nets (within the International Conference on Application and Theory of Petri Nets), pages 149-168, June 1999.
R. Wollowski and J. Beister. Comprehensive causal specification of asynchronous controller and arbiter behaviour. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 3-32. Kluwer Academic Publishers, March 2000.
Jae-Hee Won and Kiyoung Choi. Low power self-timed floating-point divider in 0.25um technology. In Proc. European Solid-State Circuits Conference (ESSCIRC), September 2000. (PDF)
Jae-Hee Won and Kiyoung Choi. Low power self-timed radix-2 division. In International Symposium on Low Power Electronics and Design, pages 210-212, July 2000.
Catherine G. Wong and Alain J. Martin. Data-driven process decomposition for the synthesis of asynchronous circuits. In IEEE International Conference on Electronics, Circuits and Systems, 2001. (PostScript)
Catherine G. Wong and Alain J. Martin. High-level synthesis of asynchronous systems by data-driven decomposition. In Proc. ACM/IEEE Design Automation Conference, pages 508-513, June 2003.
J. V. Woods, P. Day, S. B. Furber, J. D. Garside, N. C. Paver, and S. Temple. AMULET1: An asynchronous ARM processor. IEEE Transactions on Computers, 46(4):385-398, April 1997.
Sheng-Fu Wu and P. David Fisher. Automating the design of asynchronous sequential logic circuits. IEEE Journal of Solid-State Circuits, 26(3):364-370, March 1991.
Tsung-Yi Wu, Tzu-Chie Tien, A.C.-H. Wu, and Young-Long Lin. A synthesis method for mixed synchronous/asynchronous behavior. In Proc. European Conference on Design Automation (EDAC), pages 277-281, 1994.
Tzyh-Yung Wuu and Sarma B. K. Vrudhula. A design of a fast and area efficient multi-inputMuller C-element. IEEE Transactions on VLSI Systems, 1(2):215-219, June 1993.
Fei Xia and Ian Clark. Complementing role models with Petri nets in studying asynchronous data communications. In International Conference on Applications and Theory of Petri nets, pages 66-85, June 1998. (PostScript)
F. Xia and I. Clark. Complementing role models with Petri nets in studying asynchronous data communications. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 33-50. Kluwer Academic Publishers, March 2000.
F. Xia, A. Yakovlev, D. Shang, A. Bystrov, A. Koelmans, and D. J. Kinniment. Asynchronous communication mechanisms using self-timed circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 150-159. IEEE Computer Society Press, April 2000.
Aiguo Xie and Peter A. Beerel. Symbolic techniques for performance analysis of timed systems based on average time separation of events. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 64-75. IEEE Computer Society Press, April 1997.
Aiguo Xie and Peter A. Beerel. Accelerating Markovian analysis of asynchronous systems using string-based state compression. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 247-260, 1998.
Aiguo Xie and Peter A. Beerel. Accelerating Markovian analysis of asynchronous systems using state compression. IEEE Transactions on Computer-Aided Design, 18(7):869-888, July 1999.
A. Xie and P. A. Beerel. Performance analysis of asynchronous circuits and systems using stochastic timed Petri nets. In A. Yakovlev, L. Gomes, and L. Lavagno, editors, Hardware Design and Petri Nets, pages 239-268. Kluwer Academic Publishers, March 2000.
Aiguo Xie, Sangyun Kim, and Peter A. Beerel. Bounding average time separations of events in stochastic timed Petri nets with choice. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 94-107, April 1999.
G. Y. Yacoub and W. H. Ku. Self-timed simultaneous bidirectional signalling for IC systems. In Proc. International Symposium on Circuits and Systems, volume 6, pages 2957-2960, 1992.
A. V. Yakovlev and A. M. Koelmans. Petri nets and digital hardware design. In Lectures on Petri Nets II: Applications. Advances in Petri Nets, volume 1492 of Lecture Notes in Computer Science, pages 154-236, 1998.
A. Yakovlev, L. Lavagno, and A. Sangiovanni-Vincentelli. A unified signal transition graph model for asynchronous control circuit synthesis. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 104-111. IEEE Computer Society Press, November 1992.
A. V. Yakovlev, A. Petrov, and L. Rosenblum. Synthesis of asynchronous control circuits from symbolic signal transition graphs. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 71-85. Elsevier Science Publishers, 1993.
A. Yakovlev, M. Kishinevsky, A. Kondratyev, and L. Lavagno. OR causality: modelling and hardware implementation. In Proceedings of the 15th International Conference on Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, pages 568-587, Zaragosa, Spain, June 1994. Springer-Verlag. (PostScript)
Alexandre Yakovlev, Alexei Petrov, and Luciano Lavagno. A low latency asynchronous arbitration circuit. IEEE Transactions on VLSI Systems, 2(3):372-377, September 1994.
A. Yakovlev, V. Varshavsky, V. Marakhovsky, and A. Semenov. Designing an asynchronous pipeline token ring interface. In Asynchronous Design Methodologies, pages 32-41. IEEE Computer Society Press, May 1995.
Alexandre V. Yakovlev, Albert M. Koelmans, and Luciano Lavagno. High-level modeling and design of asynchronous interface logic. IEEE Design & Test of Computers, 12(1):32-40, Spring 1995.
A. V. Yakovlev, A. M. Koelmans, A. Semenov, and D. J. Kinniment. Modelling, analysis and synthesis of asynchronous control circuits using Petri nets. Integration, the VLSI journal, 21(3):143-170, December 1996.
Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, and Marta Pietkiewicz-Koutny. On the models for asynchronous circuit behaviour with OR causality. Formal Methods in System Design, 9(3):189-233, 1996.
Alexandre Yakovlev, Luciano Lavagno, and Alberto Sangiovanni-Vincentelli. A unified signal transition graph model for asynchronous control circuit synthesis. Formal Methods in System Design, 9(3):139-188, 1996.
A. Yakovlev, F. Xia, and D. Shang. Synthesis and implementation of a signal-type asynchronous data communication mechanism. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 127-136. IEEE Computer Society Press, March 2001.
Alexandre Yakovlev. Designing self-timed systems. VLSI Systems Design, 6:70-90, September 1985.
Alexandre V. Yakovlev. A relation-based approach to analysing semantics of asynchronous hardware specifications. Technical Report No. 286, University of Newcastle upon Tyne, November 1989.
Alexandre V. Yakovlev. On limitations and extensions of STG model for designing asynchronous control circuits. In Proc. International Conf. Computer Design (ICCD), pages 396-400. IEEE Computer Society Press, October 1992.
A. Yakovlev. Structural technique for fault-masking in asynchronous interfaces. IEE Proceedings, Computers and Digital Techniques, E-140(2):81-91, March 1993.
A. Yakovlev. Designing control logic for counterflow pipeline processor using Petri nets. Technical Report TR 522, Dept. of Computing Science, Univ. of Newcastle upon Tyne, 1995.
Alexandre Yakovlev. Designing control logic for counterflow pipeline processor using Petri nets. Formal Methods in System Design, 12(1):39-71, January 1998.
Teruhiko Yamada, Tsuneto Hanashima, Yasuhiro Suemori, and Masaaki Maezawa. On testing of Josephson logic circuits consisting of RSFQ dual-rail logic gates. In Proc. of the Asian Test Symposium, December 1998.
Tetsuo Yamasaki, Kenji Shima, Shinji Komori, Hidehiro Takata, Toshiyuki Tamura, Fumiyasu Asai, Takio Ohno, Osamu Tomisawa, and Hiroaki Terada. VLSI implementation of a variable-length pipeline scheme for data-driven processors. IEEE Journal of Solid-State Circuits, 24(4):933-937, August 1989.
Jing-Ling Yang, Chiu-Sing Choy, and Cheong-Fat Chan. A self-timed divider using a new fast and robust pipeline scheme. IEEE Journal of Solid-State Circuits, 36(6):917-923, 2001.
J. T. Yantchev and I. Nedelchev. Implementation of packet switching devices as delay-insensitive circuits. In Proc. Research on Integrated Systems '93. MIT Press, 1993.
J. T. Yantchev, C. G. Huang, M. B. Josephs, and I. M. Nedelchev. Low-latency asynchronous FIFO buffers. In Asynchronous Design Methodologies, pages 24-31. IEEE Computer Society Press, May 1995.
Gin Yee and Carl Sechen. Clock-delayed domino for dynamic circuit design. IEEE Transactions on VLSI Systems, 8(4):425-430, August 2000.
O. Yenersoy. Synthesis of asynchronous machines using mixed-operation mode. IEEE Transactions on Computers, 28(4):325-329, 1979.
Jeff Yetter, Bob Miller, William Jaffe, and Eric DeLano. A 100MHz superscalar PA-RISC CPU/coprocessor chip. In 1992 Symposium on VLSI Circuits Digest of Technical Papers, pages 12-13, 1992.
Chantal Ykman-Couvreur and Bill Lin. Efficient state assignment framework for asynchronous state graphs. In Proc. International Conf. Computer Design (ICCD), pages 692-697. IEEE Computer Society Press, 1995.
Chantal Ykman-Couvreur and Bill Lin. Optimised state assignment for asynchronous circuit synthesis. In Asynchronous Design Methodologies, pages 118-127. IEEE Computer Society Press, May 1995.
Chantal Ykman-Couvreur, Bill Lin, Gert Goossens, and Hugo De Man. Synthesis and optimization of asynchronous controllers based on extended lock graph theory. In Proc. European Conference on Design Automation (EDAC), pages 512-517. IEEE Computer Society Press, February 1993.
Chantal Ykman-Couvreur, Bill Lin, and Hugo de Man. Assassin: A synthesis system for asynchronous control circuits. Technical report, IMEC, September 1994. User and Tutorial manual.
M. Yoeli and A. Ginzburg. Petri-net based verification of asynchronous circuits. Technical Report CS0959, Dept. Comp. Science, Technion, Haifa, Israel, 1999. (PostScript)
Michael Yoeli and Abraham Ginzburg. LOTOS/CADP-based verification of asynchronous circuits. Technical Report CS-2001-09, Dept. Comp. Science, Technion, Haifa, Israel, 2001. replaces the earlier version CS-1998-0951. (PostScript)
M. Yoeli and E. Kohn. Petrify-based verification of asynchronous circuits. Technical Report CS-2000-02, Dept. Comp. Science, Technion, Haifa, Israel, 2000. (PostScript)
Michael Yoeli. Specification and verification of asynchronous circuits using marked graphs. In K. Voss, H. J. Genrich, and G. Rozenberg, editors, Concurrency and Nets, Advances in Petri Nets, pages 605-622. Springer-Verlag, 1987.
Michael Yoeli. Structured design of the control parts of self-timed VLSI systems. In Proc. Second International Conference on Computers and Applications, pages 839-841, Beijing, June 1987.
Michael Yoeli. Net-based synthesis of delay-insensitive circuits. Technical Report 609, Dept. Comp. Science, Technion, Haifa, Israel, 1990.
Michael Yoeli. Modulo-3 transition counter: A case study in LOTOS-based verification. Technical Report CS0950, Dept. Comp. Science, Technion, Haifa, Israel, 1998. (PostScript)
Michael Yoeli. Decompositions of asynchronous circuits. Technical Report CS-2001-16, Dept. Comp. Science, Technion, Haifa, Israel, 2001. (PostScript)
Michael Yoeli. Examples of LOTOS-based verification of asynchronous circuits. Technical Report CS-2001-08, Dept. Comp. Science, Technion, Haifa, Israel, 2001. (PostScript)
Tomohiro Yoneda and Hiroshi Ryu. Timed trace theoretic verification using partial order reduction. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 108-121, April 1999.
T. Yoneda and T. Yoshikawa. Using partial orders for trace theoretic verification of asynchronous circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996.
T. Yoneda, A. Shibayama, and T Nanya. Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan (USA), 28(8):33-43, July 1997.
T. Yoneda, M. Saarepera, and Y. Ohtsuka. Verification of parameterized asynchronous circuits: A case study. In Int. Conf. on Application of Concurrency to System Design, March 1998.
T. Yoneda, B. Zhou, and H. Schlingloff. Verification of bounded delay asynchronous circuits with timed traces. In Proceedings of AMAST98, volume 1548 of Lecture Notes in Computer Science, pages 59-73, 1999.
T. Yoneda, H. Onda, and C. Myers. Synthesis of speed independent circuits based on decomposition. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 135-145. IEEE Computer Society Press, April 2004.
Richard York. Branch prediction strategies for low power microprocessor design. Master's thesis, Department of Computer Science, University of Manchester, 1994. (PostScript)
S. Yorozu, Y. Kameda, and S. Tahara. 60 Gbps throughput demonstration of an asynchronous SFQ-pulse arbitration circuit. IEEE Transactions on Applied Superconductivity, 11(1):621-624, March 2001.
N. Yoshikawa, Z. J. Deng, S. R. Whiteley, and T. Van Duzer. Data-driven self-timed RSFQ demultiplexer. Applied Superconductivity, 6(7-9):361-365, 1998.
Hiroyasu Yoshizawa, Kenji Taniguchi, and Kenichi Nakashi. An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic. In Proc. International Symposium on Circuits and Systems, pages 145-148, June 1998.
Meng-Lin Yu and P. A. Subrahmanyan. A path oriented approach for reducing hazards in asynchronous designs. In Proc. ACM/IEEE Design Automation Conference, pages 239-244, 1992.
Meng-Lin Yu and P. A. Subrahmanyan. Hazard-free asynchronous circuit synthesis. In S. Furber and M. Edwards, editors, Asynchronous Design Methodologies, volume A-28 of IFIP Transactions, pages 87-105. Elsevier Science Publishers, 1993.
Z. C. Yu, S. B. Furber, and L. A. Plana. An investigation into the security of self-timed circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 206-215. IEEE Computer Society Press, May 2003.
Kenneth Y. Yun and David L. Dill. Automatic synthesis of 3D asynchronous state machines. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 576-580. IEEE Computer Society Press, November 1992. (PostScript) (PDF)
Kenneth Y. Yun and David L. Dill. Unifying synchronous/asynchronous state machine synthesis. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 255-260. IEEE Computer Society Press, November 1993. (PostScript) (PDF)
Kenneth Y. Yun and David L. Dill. A high-performance asynchronous SCSI controller. In Proc. International Conf. Computer Design (ICCD), pages 44-49. IEEE Computer Society Press, 1995. (PostScript) (PDF)
Kenneth Y. Yun and David L. Dill. Automatic synthesis of extended burst-mode circuits: Part i (specification and hazard-free implementation). IEEE Transactions on Computer-Aided Design, 18(2):101-117, February 1999. (PostScript) (PDF)
Kenneth Y. Yun and David L. Dill. Automatic synthesis of extended burst-mode circuits: Part ii (automatic synthesis). IEEE Transactions on Computer-Aided Design, 18(2):118-132, February 1999. (PostScript) (PDF)
Kenneth Y. Yun and Ryan P. Donohue. Pausible clocking: A first step toward heterogeneous systems. In Proc. International Conf. Computer Design (ICCD), October 1996. (PostScript) (PDF)
Kenneth Y. Yun and A. E. Dooply. Pausible clocking-based heterogeneous systems. IEEE Transactions on VLSI Systems, 7(4):482-488, December 1999.
Kenneth Y. Yun, David L. Dill, and Steven M. Nowick. Synthesis of 3D asynchronous state machines. In Proc. International Conf. Computer Design (ICCD), pages 346-350. IEEE Computer Society Press, October 1992. (PostScript) (PDF)
Kenneth Y. Yun, David L. Dill, and Steven M. Nowick. Practical generalizations of asynchronous state machines. In Proc. European Conference on Design Automation (EDAC), pages 525-530. IEEE Computer Society Press, February 1993. (PostScript) (PDF)
Kenneth Y. Yun, Bill Lin, David L. Dill, and Srinivas Devadas. Performance-driven synthesis of asynchronous controllers. In Proc. International Conf. Computer-Aided Design (ICCAD), pages 550-557, November 1994. (PostScript) (PDF)
K. Y. Yun, P. A. Beerel, and J. Arceo. High-performance asynchronous pipeline circuits. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems. IEEE Computer Society Press, March 1996. (PostScript) (PDF)
K. Y. Yun, P. A. Beerel, and J. Arceo. High-performance two-phase micropipeline building blocks: double edge-triggered latches and burst-mode select and toggle circuits. IEE Proceedings, Circuits, Devices and Systems, 143(5):282-288, October 1996. (PostScript)
Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, and Julio Arceo. A low-control-overhead asynchronous differential equation solver. In Proc. European Solid-State Circuits Conference (ESSCIRC), pages 352-355. Editions Frontières, September 1996. (PostScript) (PDF)
Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, and Julio Arceo. The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 140-153. IEEE Computer Society Press, April 1997. (PostScript) (PDF)
Kenneth Y. Yun, Peter A. Beerel, Vida Vakilotojar, Ayoob E. Dooply, and Julio Arceo. The design and verification of a high-performance low-control-overhead asynchronous differential equation solver. IEEE Transactions on VLSI Systems, 6(4):643-655, December 1998. (PostScript) (PDF)
Kenneth Y. Yun, Supratik Chakraborty, Kevin W. James, Robert Fairle-Cuninghame, and Rene L. Cruz. A self-timed real-time sorting network. In Proc. International Conf. Computer Design (ICCD), pages 427-434, October 1998. (PostScript) (PDF)
Kenneth Y. Yun, Bill Lin, David L. Dill, and Srinivas Devadas. BDD-based synthesis of extended burst-mode controllers. IEEE Transactions on Computer-Aided Design, 17(9):782-792, September 1998. (PostScript) (PDF)
Kenneth Y. Yun, Kevin W. James, Robert H. Fairle-Cuninghame, Supratik Chakraborty, and Rene L. Cruz. A self-timed real-time sorting network. IEEE Transactions on VLSI Systems, 8(3):356-363, June 2000.
Kenneth Yi Yun. Synthesis of Asynchronous Controllers for Heterogeneous Systems. PhD thesis, Stanford University, August 1994. (PostScript) (PDF)
Kenneth Y. Yun. Automatic synthesis of extended burst-mode circuits using generalized C-elements. In Proc. European Design Automation Conference (EURO-DAC), pages 290-295, September 1996. (PostScript) (PDF)
Hao Zheng. Specification and compilation of timed systems. Master's thesis, The University of Utah, June 1998. (PostScript) (PDF)
Hao Zheng. Modular Synthesis and Verification of Timed Circuits Using Automatic Abstraction. PhD thesis, The University of Utah, August 2001. (PostScript) (PDF)
B. Zhou and T. Yoneda. Conformance and mirroring for timed asynchronous circuits. In Proc. of Asia and South Pacific Design Automation Conference, pages 341-346, February 2001.