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Clement Jourdana
| Speaker: |
Clement Jourdana (National Institute of Applied Sciences
(INSA), Toulouse / LIME, TU/e)
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| Date: |
Wednesday September 26, 2007
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| Title: |
Reduction of
large resistive networks
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Abstract
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State
of the art integrated circuits can contain up to several kilometres of
wires. The on-chip interconnect is habitually modelled as a collection
of resistor elements to enable the electronics designer to take the
electrical properties of the wires into account during the design
process.
Due to the large amount of interconnect, the modelling process is
highly automated and frequently results in a prohibitively large
collection of resistor elements. A resistive path between all the bond
pads of an IC is modelled, resulting in a very complex and very large
resistive network. A realistic problem would include up to by and large
one thousand pads and hundreds of thousands or even millions of
resistors.
In order to be able to perform an analysis, this large collection must
first be reduced to something more manageable. The problem consists in
efficiently applying model order reduction to a very large on-chip
network. Clearly, any method has to deal with a large number of
terminals to the external world.
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