Nathaniel Egwu

The simulation of the  physical layout of parameterized cells (pcells) with  parameters as their defining properties is vital in the circuit design process. The steps involve generation of the layout by the optimization loop, extraction and netlist creation for simulation. The usual optimization of the physical layout is done several times and extraction has to be repeated at every iteration. This greatly increases the time required to extract the physical layout. We present a method that can be used to speed up extraction. The formulation is based on investigating the relationship between parameters of pcells and the parasitic capacitances obtained in the netlist.
In contrast to full extraction of the entire layout, we implement partial extraction of the layout of the individual pcells and compare the time obtained in both cases. The effects of parameters will also be classified as discrete or continuous based on the structure of the netlists created. The procedure is implemented to some pcells which form part of the low noise amplifier.
 
Some models that can be used to predict the netlist will be proposed and comparison made between the extracted values and the predicted model. This enables us to obtain the relative error between the predicted and extracted netlists which is used  to determine the accuracy of the models. For models with high accuracy, time can be saved by performing partial extraction where  there exist a significant difference between the relative error between the predicted and extracted values. This can speed  up the whole process since extraction has to be performed at specific steps during optimization.