Promoters: prof.dr. J.C.M. Baeten (TU/e and CWI) and prof.dr.ir. J.E. Rooda (TU/e)
Co-promotor: dr.ir. P.J.L. Cuijpers (TU/e)
Faculty of Mathematics and Computer Science, TU/e
Technische Universiteit Eindhoven
Date: 22 January, 2013.
This thesis addresses two particular issues related to the design of embedded systems; namely, refinement of communication and refinement of states.
The refinement of communication deals with the issue of implementing a synchronous system in an asynchronous way such that two systems are behaviourally equivalent. As a result, correctness of an asynchronous system can be achieved by establishing correctness on its synchronous version, which is computationally cheaper than analysing the latter. The research objective was to find conditions that ensure the addition of buffers do not modify the behaviour of a given synchronous system. We show that it is possible to obtain better desynchronisability conditions (even for finer equivalence like branching bisimulation) by changing the properties of the communication protocol. This is in contrast with the previous works where the focus was only on restricting the communicating components.
The refinement of states deals with the stepwise development of hybrid systems. Such a concept was absent in the Compositional Interchange Format (CIF), a modelling language for embedded systems based on hybrid automata and some process algebraic operators. The research objective was to develop a compositional operational semantics of CIF with hierarchy (HCIF). We show that by referring only to the transition system of the substructures (not to their syntactic representation), the semantics of HCIF operators is almost unchanged with respect to their CIF versions. Furthermore, a definition to eliminate hierarchy in a HCIF model is presented. As a result, the existing simulation tools and the transformation tools to other timed or hybrid languages can be reused upon the elimination of hierarchy from a HCIF model.