VLSI Programming [2IN35]

Spring 2012

Period:

BIS-1, CSE-1

Credit points:

5 ects

Provided by:

Dept W&I, CS

Teachers:

Prof.dr. C.H. van Berkel, dr. R.H. Mak

Enquiries

Prof.dr. C.H. van Berkel, dr. R.H. Mak

Instruction type:

(10 afternoons):

semester B: 4 * 2 hours lecture
semester B: 6 * (1 hour lecture + 3 hours laboratory work)

Examination:

assignments + report on lab work

Oral examination schedule:

Study material:

Keshab K. Parhi:

VLSI Digital Signal Processing Systems, Design and Implementation. Wiley Inter-Science 1999.

pdf slides with text book: html ,

same (local copies): Parhi2.pdf , Parhi3.pdf , Parhi4.pdf , Parhi5.pdf , Parhi6.pdf , Parhi7.pdf , Parhi8.pdf , Parhi9.pdf , Parhi10.pdf , Parhi11.pdf , Parhi13.pdf , Parhi14.pdf , Parhi15.pdf , Parhi16.pdf , Parhi17.pdf , Parhi18.pdf

High-Level Algorithm and Architecture Transformations for DSP Synthesis. Journal of VLSI Signal Processing, 9, 121-143 (1995), Kluwer Academic Publishers, Boston.

Keshab K. Parhi and David G. Messerschmitt, Pipeline Interleaving and Parallelism in Recursive Digital Filters - Part I: Pipelining Using Scattered Look-Ahead and Decomposition. IEEE Trans. on Acoustics, Speech, and Signal Processing, Vol. 37, No. 7, July 1989, pp 1099 - 1117.

Goals:

to acquire insight in the description, design, and optimization of fine-grained parallel computations;

to acquire insight in the (future) capabilities of VLSI as an implementation medium of parallel computations;

to acquire skills in the design of parallel computations and in their implementation on FPGAs.

Contents:
Massive parallelism is needed to exploit the huge and still increasing computational capabilities of Very Large Scale Integrated (VLSI) circuits. In this course:

we focus on fine-grained parallelism (not on networks of computers);

we assume that parallelism is by design (not by compilation);

we draw inspiration from consumer applications, such as digital TV, 3D TV, image processing, mobile phones, etc.;

we will use Field Programmable Arrays (FPGA) as fine-grained abstraction of VLSI for practical implementation.

Major elements of the course:

Classifications: linear/non-linear, time-(in)variant systems, 1D/2D.

Representations and formalisms: data flow graphs, state-space forms, transfer functions, vector-parallel programs, parallel programs.

Performance metrics and scalability: costs (silicon area), computation time (throughput), power consumption (energy).

Architectures: digital hardware, systolic arrays, VLIW, SIMD.

Design & optimization: (SW) pipelining, unfolding, retiming, re-use of partial results, vectorization, etc.

Implementation media: VLSI, FPGAs, (vector) DSPs.

Time Table:

Day Date Time Location Subject (provisional) Lab work slides

Tue Feb. 7 Hr 5 + 6 AUD. 15 introduction, DSP representations, bounds - 2IN35s1.pdf

Tue Feb. 14 Hr 5 + 6 AUD. 15 pipelining, retiming, transposition, J-slow, unfolding - -

Tue Feb. 21 - - no lecture (carnaval) have FPGA tools installed -

Tue Feb. 28 Hr 5 + 6 AUD. 15 unfolding (cntd), look-ahead, strength reduction - -

Tue Mar. 6 Hr 5 + 6 + 7 + 8 AUD. 15 Introductions FPGA, Verilog (A1) -

Tue Mar. 13 Hr 5 + 6 + 7 + 8 AUD. 15 systolic computation (A1) -
Tue Mar. 20 Hr 5 + 6 + 7 + 8 AUD. 15 folding FPGA pipelining, retiming (A2) -

Tue Mar. 27 Hr 5 + 6 + 7 + 8 AUD. 15 DSP processors FPGAs: parallelism, strength reduction (A3) -

Tue Apr. 3 Hr 5 + 6 + 7 + 8 AUD. 15 FPGAs: sample-rate conversion (A4) -

Tue Apr. 10,17 - - 2x NO LECTURE (examinations) - -

Tue Apr. 24 Hr 5 + 6 + 7 + 8 - hand-in report A3 FPGAs: video scaler (A5) -

Tue May 1 Hr 5 + 6 + 7 + 8 - FPGAs: video scaler (A5 cntd) -

Tue May. 22 - - DEADLINE final report A4, A5 - -

Lab Classes

Required software:

Install required software on your notebook before first lab class on March 9.

Q&A on required software with Tseesuren on Tue March 9.

For assignments and Lab work files,

For FPBA-board reservation for Thursday afternoon, click reserve

Opmerkingen over deze pagina zijn welkom

Day	Date	Time	Location	Subject (provisional)	Lab work	slides
Tue	Feb. 7	Hr 5 + 6	AUD. 15	introduction, DSP representations, bounds	-	2IN35s1.pdf
Tue	Feb. 14	Hr 5 + 6	AUD. 15	pipelining, retiming, transposition, J-slow, unfolding	-	-
Tue	Feb. 21	-	-	no lecture (carnaval)	have FPGA tools installed	-
Tue	Feb. 28	Hr 5 + 6	AUD. 15	unfolding (cntd), look-ahead, strength reduction	-	-
Tue	Mar. 6	Hr 5 + 6 + 7 + 8	AUD. 15	Introductions FPGA, Verilog	(A1)	-
Tue	Mar. 13	Hr 5 + 6 + 7 + 8	AUD. 15	systolic computation	(A1)	-
Tue	Mar. 20	Hr 5 + 6 + 7 + 8	AUD. 15	folding	FPGA pipelining, retiming (A2)	-
Tue	Mar. 27	Hr 5 + 6 + 7 + 8	AUD. 15	DSP processors	FPGAs: parallelism, strength reduction (A3)	-
Tue	Apr. 3	Hr 5 + 6 + 7 + 8	AUD. 15		FPGAs: sample-rate conversion (A4)	-
Tue	Apr. 10,17	-	-	2x NO LECTURE (examinations)	-	-
Tue	Apr. 24	Hr 5 + 6 + 7 + 8	-	hand-in report A3	FPGAs: video scaler (A5)	-
Tue	May 1	Hr 5 + 6 + 7 + 8		-	FPGAs: video scaler (A5 cntd)	-
Tue	May. 22	-	-	DEADLINE final report A4, A5	-	-