Test Time Reduction Algorithms for Core-Based ICs

Abstract:
As the manufacturing process of ICs is a very insecure process, every single IC is tested. The consequence is that test costs form a substantial part of the overall production costs. In this report we focus on test time reduction as a way to reduce the test costs. Test time considerations can be embedded in the design-for-testability. We analyze the test time consequences of several scan chain architectures for core-based ICs. Another approach on test time reduction is test scheduling; given a set of tests, order the tests such that the total test time is minimized. We define problem definitions for test scheduling and proof that these problems are $\mathcal{NP}$-complete. Furthermore we derive models based on standard scheduling models and describe a heuristic for test scheduling. Key words: IC test time reduction, scan chain design for core-based ICs, test scheduling, combinatorial optimization