Test Protocol Scheduling for Embedded-Core Based system ICs

Abstract:
Embedding reusable cores enables efficient design of large system ICs. We assume that cores come with pre-computed tests, which, after expansion to the IC pins, together constitute the IC test. The size of the IC-level test vector set is an important cost factor, as it determines both the required storage capacity for test vectors of the test equipment, as well as the test application time. Advanced scheduling of the various core tests at IC level can significantly reduce the test vector set without affecting the IC design nor the test quality. In this paper we describe Test Protocol Scheduling (TPS), i.e., test scheduling with expanded test protocols as basic schedule unit. Based on a property of our Test Protocol Expansion process, TPS only requires resource conflict checking at the IC pins. We describe TPS formally, show its resemblance to No-Wait Job Shop Scheduling, and present a four-step heuristic algorithm for TPS, based on pairwise composition of test protocols.