Checking and Deriving Module Paths in Verilog Cell Library Descriptions

Matthias Raffelsieper, MohammadReza Mousavi and Chris Strolenberg. Proceedings of the Conference on Design Automation and Test in Europe (DATE'2010), Dresden, Germany, ACM Press, March 2010.

Abstract

Module paths are often used to specify the delays of cells in a Verilog cell library description, which define the propagation delay for an event from an input to an output. Specifying such paths manually is an error prone task; a forgotten path is interpreted as a zero delay, which can cause further flaws in the subsequent design steps. Moreover, one can specify superfluous module paths, i.e., module paths that can never occur in any practical run of the model and hence, make excessive restrictions on the subsequent design decision. This paper presents a method to check whether the given module paths are reflected in the functional implementation. Complementing this check, we also present a method to derive module paths from a functional description of a cell.

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@InProceedings{MousaviDATE10,
    author      = "Raffelsieper, Matthias  and Mousavi, MohammadReza  and Strolenberg, Chris  and  Zantema, Hans",
    title       = "Checking and Deriving Module Paths in Verilog Cell Library Descriptions",
    booktitle   = "Proceedings of the Conference on Design Automation and Test in Europe ({DATE 2010})",
    address     = "Dresden, Germany",
    publisher  = "ACM Press",
    year        = "2010"
}

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