Name of the project

Performance analysis of hardware data structures

Background

Over the years many hardware designs have been given for data structures commonly found in algorithms, such as stacks, queues, and priority queues. The main reason for hardware implementations of these structures is performance. However, for a hardware design there are many performance metrics that can be optimized most notably area, throughput and latency, but more recently also energy consumption. Solutions that are optimal with respect to one metric are usually suboptimal with respect to another metric.

Goals and task

The goal of this project is to describe and analyze a number of hardware designs for data structures using the

Haste toolset from Handshake Solutions in search for Pareto optimal solutions.

Cooperation

None.

References

At the start of the project a number of references to articles in the literature will be provided.

Pre-requisites

Successful completion of course 2IN30 (VLSI programming).

Planning (time frame & supervisor)

The project will be supervised by Rudolf Mak from the TU/e. Duration three months (20 ects).

Status (who is doing the project; maybe a pointer to recent info)

Open for application.