In [ ]:


MSc assignments contributing to

the StaccatoLab program


Ongoing and past assignments


Author: Kees van Berkel,

  • part-time full professor of SAN (System Architecture and Networking),
  • within the department Computer Science and Mathematics of the Technical University Eindhoven,
  • email:

Date: 2018 January 3

Extend PYNQ with a dataflow interface (PYNQ = Python on Zynq)


  • The PYNQ-Z1 board is the hardware platform for the PYNQ open-source framework, and can be programmed in Jupyter Notebook using Python. The board features the ZYNQ XC7Z020 FPGA.
  • Given: a converter from StaccatoLab dataflow graphs to an equivalent Verilog description. (Work in progress.)


  • a PYNQ extension that allows the user to logic-synthesize, load, run, and debug StaccatoLab dataflow graphs,
  • ... such that all user interaction is in dataflow terms (dataflow graph, nodes, edges, tokens, ..., rather than Verilog entities, FPGA resources, ... );
  • a demonstration of this extension on a video (image stream) dataflow program on a PYNQ-Z1 board.


  • pre-study: develop a video algorithm as dataflow graph (e.g. a video scaler or a Sobel filter);
  • pre-study: develop a Python script to create an FPGA image from a Verilog program;
  • explore how logic-synthesis results can be reinterpreted in dataflow terms;
  • explore how to interact with FPGA hardware in dataflow terms: run graph, set break-point, inspect node-fsm state, inspect token, show firing rates, ..;
  • design Python scripts as PYNQ extensions (invoked from Jupyter notebook) that offer such a dataflow interface;
  • .. same, for the video algorithm;
  • develop Jupyter-based instrumentation: FPGA break-point setting, FPGA state inspection, ...


  • Python scripts for mapping, running, and instrumentation of dataflow graphs on a PYNQ-Z1;
  • a dataflow-on-PYNQ demonstrator, which can be used as basis for new assignments for the VLSI Programming course.