Dear ACID-WG colleague and/or summer school speaker, The final program for the summer school has now been finalized. I am happy about the result. At present I have broadcast it to a couple of mailing lists: - asynchronous, - EuroPractice, - "a Spanish list" provided by Jordi - I have asked Professors Mermet and Nebel to help (using their OFFIS and ECSI lists). I will bring A5 sized booklets to Async97, and I'll give each of you a pile for further distribution. Also these booklets will be "on display" at CHDL later this month. If any of you are going to relevant conferences during the next months, please bring the announcement - I can print and send you copies of the A5 booklet mentioned above. I welcome suggestions on how to spread the information further, and I encourage you to forward the announcement to relevant (industrial) contacts. - Jens Sparso +----------------------------------+---------------------------------+ | Jens Sparsoe (Assoc. Professor) | Dept. of Information Technology | +----------------------------------+ Technical University of Denmark | | Phone: +45 45 25 37 47 | Building 344 | | Fax: +45 45 93 00 74 | DK 2800 Lyngby | | E-mail: jsp@it.dtu.dk | DENMARK | +----------------------------------+---------------------------------+ S U M M E R S C H O O L on A S Y N C H R O N O U S C I R C U I T D E S I G N Technical University of Denmark, August 18-22, 1997 http://www.it.dtu.dk/~sum97/ INTRODUCTION ============ This summer school is organized by the Department of Information Technology at the Technical University of Denmark, and by ACiD-WG (Esprit Nr. 21949, Working Group on Asynchronous Circuit Design). Its aim is to stimulate experimentation with and application of methods and tools for the design of asynchronous circuits. The target audience comprises (1) Ph.D. students from Computer Science and Electrical Engineering departments, and (2) researchers, architects and designers in the electronics industry. The summer school will provide insight into and hands on experience with state-of-the-art design methods and CAD-tools for asynchronous design. ASYNCHRONOUS CIRCUITS ===================== Asynchronous circuits operate without a global clock signal - the flow of data is controlled by local handshaking between subsystems at all levels in the design. This gives asynchronous circuits some unique characteristics that can be exploited to advantage. Asynchronous circuits may be faster, consume less power, avoid electro-magnetic emission of clock harmonics, and may offer natural solutions in multi-clock environments. Indeed chips have been fabricated that demonstrate these characteristics. A general understanding of where and how to exploit asynchronous techniques is evolving out of worldwide research activities undertaken by both academia and industry. CAD tools for synthesis and analysis are also emerging. Asynchronous logic can be expected to find niches in the digital electronics business over the next few years. It will share circuit boards with clocked chips and integrated circuits with clocked subcircuits. It will become established as a viable alternative technology in many areas, and the technology of choice for some. This summer school will expose its participants to asynchronous circuit design, so as to stimulate further research and development and to encourage commercial use of asynchronous design techniques. PROGRAM ======= Rather than attempting a comprehensive coverage of the field, the summer school lectures will provide in-depth coverage of a few of the more significant approaches to asynchronous design. There will be plenty of opportunity for hands-on experience with the associated CAD tools. Furthermore, the summer school has been planned as one coordinated event where the different parts complement each other. The program reflects a bottom-up approach to asynchronous design with a significant element of practical CAD-tool laboratories. P1. Introduction (0.5 day) ------------------------- Professor Steve Furber from Manchester University will open the summer school and give an introduction to asynchronous circuit design. The presentation will cover motivation, basic concepts, design and circuit implementation styles. It will conclude with some example circuits that can be designed by hand. The purpose is to build an intuition and a basic understanding of asynchronous design. The presentation will have a self-contained non-theoretical flavour. P2. Fundamental Concepts (0.5 day) --------------------------------- A number of issues that are fundamental to asynchronous design will be explained in depth: (1) isochronic forks and logic thresholds, (2) arbitration and metastability, (3) hazards and races, and (4) design styles for asynchronous control circuits - similarities and differences. Steve Furber will cover topics 1 and 2. Michael Kishinevsky will cover topics 3 and 4. P3. Synthesis of control circuits from STG specifications (1 day). ----------------------------------------------------------------- Signal Transition Graphs are a class of Petri net that can be used to specify asynchronous control circuits. Within the last couple of years significant progress has been made - theoretical problems have been solved, and CAD tools have been developed. Dr. Michael Kishinevsky and Dr. Jordi Cortadella are part of an active and successful collaborative research effort involving the University of Aizu and ACiD-WG. They will expose participants to the STG formalism and to the synthesis tool Petrify. P4. Tangram silicon compiler (2 days). ------------------------------------- At Philips Research Laboratories Dr. Kees van Berkel and his co-workers have developed a language (Tangram) and a silicon compiler for the design of asynchronous circuits. Within Philips, their VLSI programming approach has been followed in several industrial-scale designs. At the summer school Kees van Berkel and Joep Kessels will give an in-depth introduction to Tangram. It will cover the whole picture from specification to circuit implementation, and will include hands-on experience with Tangram and small design projects. P5. Recent asynchronous Integrated Circuits. ------------------------------------------- Several of the partners in ACiD-WG have designed and fabricated nontrivial asynchronous IC's: At Philips a number of IC's for different consumer products, at the University of Manchester several asynchronous versions of the ARM microprocessor, and at the Technical University of Denmark a DSP circuit for a hearing aid. A number of short presentations will explain the characteristics of these IC's, relate the results to corresponding synchronous designs, and discuss the experiences and lessons learned. LECTURE PLAN ============ Note that about half of the lecture slots P3.1-4 and P4.1-8 will be used for practical work (demos, labs, and small design projects). Participants will work in teams of 2-3 people. +-------------+----------+----------+----------+----------+----------+ | Time | Monday | Tuesday | Wednesday| Thursday | Friday | |=============|==========|==========|==========|==========|==========| | | (1)| (5)| (9)| (12)| (16)| | 9:00-10:30 | P1.1 | P3.2 | P4.4 | P3.4 | P2.2 | | | SBF | MK/JC | KvB/JK | MK/JC | SBF | +-------------+----------+----------+----------+----------+----------+ | 10:30-11:00 | COFFEE AND TEA | +-------------+----------+----------+----------+----------+----------+ | | (2)| (6)| (10)| (13)| (17)| | 11:00-12:30 | P1.2 | P4.2 | P4.5 | P2.1 | P4.8 | | | SBF | KvB/JK | KvB/JK | MK | KvB/JK | +-------------+----------+----------+----------+----------+----------+ | 12:30-14:00 | LUNCH | +-------------+----------+----------+----------+----------+----------+ | | (3)| (7)| P5.1 (11)| (14)| (18)| | 14:00-15:30 | P3.1 | P3.3 | SBF/KvB, | P4.6 | Design | | | MK/JC | MK/JC | JS/et al.| KvB/JK | Reviews | +-------------+----------+----------+----------+----------+ | | 15:30-16:00 | COFFEE AND TEA | CLOSING | +-------------+----------+----------+----------+----------+----------+ | | (4)| (8)| Sight- | (15)| | 16:00-17:30 | P4.1 | P4.3 | seeing | P4.7 | | | KvB/JK | KvB/JK | Copen- | KvB/JK | +=============+==========+==========+ hagen +==========+ +-------------+----------+----------+ + +----------+ | | | | Summer | | | 19:00- | Informal | (Labs | School | (Labs | | | Dinner | open) | Dinner | open) | +-------------+----------+----------+----------+----------+ Speaker initials: SBF = Steve B. Furber MK = Michael Kishinevsky JC = Jordi Cortadella KvB = Kees van Berkel JK = Joep Kessels JS = Jens Sparso SPEAKER BIOGRAPHIES =================== Kees van Berkel (KvB) --------------------- Kees van Berkel is a senior scientist at the IC Design Center of Philips Research Laboratories, Eindhoven, where he coordinates the work on VLSI programming and asynchronous circuits. He is also parttime Professor at Eindhoven University of Technology. He received his M.Sc. (honours) degree in EE from Delft University of Technology and his Ph.D. degree from EUT. He was manager of the ESPRIT OMI/EXACT project ('92-'95) that focused on Exploitation of Asynchronous Circuit Technologies, and he is Program Co-chair of Async'97, the Third International Symposium on Advanced Research in Asynchronous Circuits and Systems. Kees van Berkel is author of the book "Handshake Circuits - An Asynchronous Architecture for VLSI Programming." Jordi Cortadella (JC) --------------------- Jordi Cortadella received his M.Sc. and Ph.D. degrees in Computer Science from the Polytechnic University of Catalonia, Barcelona, Spain, in 1985 and 1987. He is an Associate Professor at the Department of Computer Architecture, Polytechnic University of Catalonia. In 1988, he was a Visiting Scholar at the University of California, Berkeley. His research interests include computer-aided design of VLSI systems with special emphasis on synthesis and verification of asynchronous circuits, computer arithmetic and parallel architectures. Prof. Cortadella has co-authored more than 50 research papers in technical journals and conferences. Steve B. Furber (SBF) --------------------- Steve Furber received his B.A. degree in Mathematics in 1974 and his Ph.D. in Aerodynamics in 1980 from the University of Cambridge, England. From 1980 to 1990 he worked in the hardware development group within the R&D department at Acorn Computers Ltd., and was a principal designer of the BBC Microcomputer and the ARM 32-bit RISC microprocessor, both of which earned Acorn Computers a Queen's Award for Technology. Since moving to the ICL chair of Computer Engineering at the University of Manchester in 1990, he has established a research group with interests in asynchronous logic design and power-efficient computing. He is a Fellow of the British Computer Society and a Chartered Engineer. Joep Kessels (JK) ----------------- Joep Kessels is a senior scientist at the Philips Research Laboratories, Eindhoven, where he was involved in projects on applicative programming, distributed processing, and local area networks. Currently he is engaged in a project on VLSI programming of asynchronous circuits. In this project he designed several chips, two of which perform error correction in a DCC player. His main research topics are design methodology and distributed processing. Michael Kishinevsky (MK) ------------------------ Michael Kishinevsky holds his M.Sc. and Ph.D. degrees in Computer Science from the Electrotechnical University of St. Petersburg, Russia. He has been a researcher at the Russian Academy of Science and has worked with R&D Coop TRASSA. From 1992 to 1994 he was a visiting Associate Professor at the Department of Computer Science, Technical University of Denmark. Since the end of 1994 he has been a Professor at the University of Aizu, Japan. His present research interests are in the field of design of asynchronous and reactive systems and in the theory of concurrency. He has co-authored two books and more than 40 papers on asynchronous design and concurrency. Jens Sparso (JS) ---------------- Jens Sparso received his M.Sc. degree in Electrical Engineering from the Technical University of Denmark in 1981. Since 1982 he has been with the Department of Information Technology at the Technical University of Denmark, where he became Associate Professor in 1986. In the 1995-96 academic year he was visiting Associate Professor at the Computer Science Department, University of Utah. His research interests are architecture and design of VLSI systems, i.e. design methods, circuit techniques, and the interplay between technology and system architecture. Current emphasis is on asynchronous circuits and circuits with low power consumption. Prof. Sparso has given tutorials on asynchronous circuit design at several conferences. LOCATION ======== The summer school takes place on campus at the Technical University of Denmark in Lyngby. Lyngby is a suburb of Copenhagen 10 kilometres north of the city centre and is easily reached by public transportation from Copenhagen airport and from the central railway station of Copenhagen. Details regarding transportation can be found on the summer school web-pages where you will also find maps of the campus and the Lyngby area. LECTURE NOTES ============= A set of lecture notes will be compiled and handed out at the summer school. The lecture notes will consist of notes prepared for the summer school, previously published papers, and slides. REGISTRATION INFORMATION ======================== The registration fee is 1,500 DKK, and this covers lunch and coffee/tea during the summer school, the two dinners, and printed material. The deadline for registration is July, 11. In case of cancellation before August 4, the fee will be refunded less an administrative charge of 300 DKK. No refund will be made after this date. The number of participants is limited to 50. In case we need to enforce that limit, the decision will be based on the order in which we receive registrations, combined with an attempt to accommodate participants from as many institutions as possible. STUDENT TRAVEL GRANTS ===================== Prospective participants from institutions that are not members of ACiD-WG may apply for travel grants. A travel grant application should contain name, address, e-mail, fax, nationality, age, type of student (full time, part time, undergraduate, postgraduate), student status confirmed by responsible university supervisor, academic profile, and estimated travel costs. The application should be sent to Prof. Jens Sparso, and it should arrive no later than June 20. Applicants will be informed of the decision regarding their application around July 4. ACCOMMODATION ============= Participants are expected to make their own arrangements for accommodation. Information about two hotels in the vicinity of the campus is available below, but there are many more options. The two hotels are Hotel Eremitage and Hotel Fortunen. Blocks of rooms have been reserved at these hotels. Reservations should be made before July 11, and you should refer to "Async. Summer School" when making a reservation. HOTEL EREMITAGE Klampenborgvej Lyngby Storcenter 62 tel. +45 4588 7700 Single: 710 DKK DK-2800 Lyngby fax. +45 4588 1782 Double: 825 DKK DENMARK HOTEL FORTUNEN Single (without bath): 315 DKK Ved Fortunen 33 tel. +45 4587 0073 Single : 473 DKK DK-2800 Lyngby fax. +45 4587 1222 Double (without bath): 495 DKK DENMARK Double : 653 DKK The hotels are very different, but both of high quality. Hotel Eremitage is a modern hotel in the middle of a commercial center in Lyngby. Hotel Fortunen is an older small hotel located next to a large forest. Both hotels are within walking distance (20 minutes) of the campus. At the time of the summer school, the University is expected to have a limited number of rooms in student housing - single and double rooms sharing bath and kitchen. The rooms are currently being refurbished to a high standard. We expect rates around 100 DKK per person per night. Inquiries concerning these rooms should be addressed to the summer school secretary, Ms. Disa la Cour. MORE INFORMATION ================ This announcement and additional information related to travel and accommodation may be found on the summer school web-pages. ORGANIZATION ============ Directors: Prof. Jens Sparso Technical University of Denmark Prof. Jorgen Staunstrup Technical University of Denmark Dr. Mark B. Josephs ACiD-WG Project Manager Local organization: e-mail: Phone: Prof. Jens Sparso jsp@it.dtu.dk +45 4525 3747 Prof. Jorgen Staunstrup jst@it.dtu.dk +45 4525 3740 Secretary: Ms. Disa la Cour sum97@it.dtu.dk +45 4525 3722 Address: Department of Information Technology Technical University of Denmark Building 344 DK-2800 Lyngby DENMARK FAX: +45 4593 0074 WWW: http://www.it.dtu.dk/~sum97/ (Summer School) http://www.scism.sbu.ac.uk/ccsv/ACiD-WG/ (ACiD-WG) -------------------------- REGISTRATION FORM ------------------------- REGISTRATION FORM SUMMER SCHOOL ON ASYNCHRONOUS CIRCUIT DESIGN Technical University of Denmark, August 18-22, 1997 First Name . . . . . . . . . . . . . . . . . . . . . . . . . . . Family Name. . . . . . . . . . . . . . . . . . . . . . . . . . . Prof.Dr.Mr.Ms.: . . . . . . . . . . . . . . . . . . . . . . . . Affiliation. . . . . . . . . . . . . . . . . . . . . . . . . . . Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tel: . . . . . . . . . . . . . . . . . . . . . . . . Fax: . . . . . . . . . . . . . . . . . . . . . . . . E-mail:. . . . . . . . . . . . . . . . . . . . . . . Your identification as it should appear on your badge: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diet (Standard, Vegetarian, Diabetic): . . . . . . . . . . . . . Method of Payment (please check (X) the appropriate): ( ) I enclose a copy of bank transfer of 1,500 DKK to: Bank name: Den Danske Bank, DTU branch Address: DTU, Building 101 DK-2800 Lyngby DENMARK Account No.: 4263 972007 Reference: 95-639000-149-31-3591-149985 "Async. Summer School" ( ) I enclose a bank check of 1,500 DKK issued to: "Async. Summer School" Dept. of Information Technology DTU, Building 344 DK-2800 Lyngby DENMARK REGISTRATION DEADLINE: July 11, 1997 -------------------- END OF REGISTRATION FORM --------------------------